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dual interface for flat panel display ad9887a rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2003C2007 analog devices, inc. all rights reserved. features analog interface 170 msps maximum conversion rate programmable analog bandwidth 0.5 v to 1.0 v analog input range 500 ps p-p pll clock jitter at 170 msps 3.3 v power supply full sync processing midscale clamping 4:2:2 output format mode digital interface dvi 1.0-compatible interface 170 mhz operation (2 pixels/clock mode) high skew tolerance of 1 full input clock sync detect for hot plugging supports high bandwidth digital content protection applications rgb graphics processing lcd monitors and projectors plasma display panels scan converters microdisplays digital tvs general description the ad9887a offers an analog interface receiver and a digital visual interface (dvi) receiver integrated on a single chip, supports high bandwidth digital content protection (hdcp), and is software and pin-to-pin compatible with the ad9887. analog interface the complete 8-bit, 170 msps, monolithic analog interface is optimized for capturing rgb graphics signals from personal computers and workstations. its 170 msps encode rate capability and full-power analog bandwidth of 330 mhz support resolutions of up to 1600 1200 (uxga) at 60 hz. the interface includes a 170 mhz triple adc with internal 1.25 v reference; a phase- locked loop (pll); and programmable gain, offset, and clamp controls. the user provides only a 3.3 v power supply, analog input, and hsync. three-state cmos outputs can be powered from 2.5 v to 3.3 v. the analog interface also offers full sync processing for composite sync and sync-on-green (sog) appli- cations. the ad9887a on-chip pll generates a pixel clock from hsync with output frequencies ranging from 12 mhz to 170 mhz. pll clock jitter is typically 500 ps p-p at 170 msps. functional block diagram 0 2838-001 hsync coast clamp ckinv ckext filt vsync serial register and power management scl sda a1 a0 datack hsout vsout sogout rx0+ rx0? rx1+ rx1? rx2+ rx2? rxc+ rxc? dvi receiver ad9887a digital interface sync processing and clock generation analog interface s cdt refin ddcscl ddcsda mcl mda hdcp sogin red a red b green a green b blue a blue b hsout vsout sogout de datack refout muxes r ain clamp 8 8 8 g ain clamp 8 8 8 b ain clamp 8 8 8 2 datack 2 ref r outa r outb g outa g outb b outa 8 8 8 8 8 8 2 8 8 8 8 8 8 8 8 8 r outa r outb g outa g outb b outa b outb rterm de hsout vsout a/d a/d a/d figure 1. digital interface the ad9887a contains a dvi 1.0-compatible receiver and supports resolutions up to 1600 1200 (uxga) at 60 hz. the receiver operates with true color (24-bit) panels in one or two pixel(s) per clock mode and features an intrapair skew tolerance of up to one full clock cycle. with the inclusion of hdcp, displays can receive encrypted video content. the ad9887a allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewability of authentication during transmission, as specified by the hdcp v1.0 protocol. fabricated in an advanced cmos process, the ad9887a is provided in a 160-lead, surface-mount, plastic mqfp and is specified over the 0c to 70c temperature range. the ad9887a is also available in an rohs compliant package.
ad9887a rev. b | page 2 of 52 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 analog interface ........................................................................... 3 digital interface ............................................................................ 5 absolute maximum ratings ............................................................ 7 explanation of test levels ........................................................... 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 pin function detailspins shared between digital and analog interfaces ........................................................................ 11 pin function detailsanalog interface ................................. 13 pin function detailsdigital interface .................................. 16 theory of operation and design guideanalog interface .... 17 general description ................................................................... 17 input signal handling ................................................................ 17 hsync and vsync inputs ...................................................... 17 clamping ..................................................................................... 17 gain and offset control ............................................................ 18 sync-on-green input ................................................................. 19 clock generation ....................................................................... 19 alternate pixel sampling mode ................................................ 22 timinganalog interface ........................................................ 23 theory of operationinterface detection ................................ 27 active interface detection and selection ................................ 27 hot-plug detect .......................................................................... 27 power management ................................................................... 27 scan function ............................................................................. 28 theory of operationdigital interface ...................................... 29 capturing encoded data ........................................................... 29 data frames ................................................................................ 29 special characters ...................................................................... 29 channel resynchronization ...................................................... 29 data decoder .............................................................................. 29 hdcp .......................................................................................... 29 general timing diagramsdigital interface ............................ 31 timing mode diagramsdigital interface ........................... 31 2-wire serial register map ........................................................... 32 2-wire serial control register details .................................... 35 theory of operationsync processing ...................................... 48 sync stripper ............................................................................... 48 sync separator ............................................................................ 48 pcb layout recommendations .................................................... 49 analog interface inputs ............................................................. 49 digital interface inputs .............................................................. 49 power supply bypassing ............................................................ 49 pll ............................................................................................... 50 outputsboth data and clocks .............................................. 50 digital inputs .............................................................................. 50 volt age reference ....................................................................... 50 outline dimensions ....................................................................... 51 ordering guide .......................................................................... 51 revision history 3/07rev. a to rev. b changes to figure 1.......................................................................... 1 changes to figure 28...................................................................... 27 changes to figure 37 and figure 40............................................. 31 12/05rev. 0 to rev. a updated format..................................................................universal added pb-free package .....................................................universal changes to figure 1.......................................................................... 1 changes to specifications ................................................................ 4 changes to table 4.......................................................................... 10 deleted analog interface pin list table ...................................... 11 added figure 3................................................................................ 18 added tv section in table 7........................................................ 22 deleted digital interface pin list table....................................... 24 changes to theory of operation (interface detection) section........................................................ 28 added hot-plug detect section ................................................... 28 changes to table 8.......................................................................... 29 changes to figure 32...................................................................... 32 changes to control bits section................................................... 44 change to figure 42 ....................................................................... 48 updated outline dimensions....................................................... 53 changes to ordering guide .......................................................... 53 5/03revision 0: initial version
ad9887a rev. b | page 3 of 52 specifications analog interface v d = 3.3 v, v dd = 3.3 v, adc clock = maximum conversion rate, unless otherwise noted. table 1. ad9887aks-100 ad9887aks-140 ad9887aks-170 parameter temp test level min typ max min typ max min typ max unit resolution 8 8 8 bits dc accuracy differential nonlinearity 25c i 0.5 +1.15/?1.0 0.5 +1.25/?1.0 0.8 +1.25/?1.0 lsb full vi +1.15/?1.0 +1.25/?1.0 +1.50/?1.0 lsb integral nonlinearity 25c i 0.5 1.40 0.5 1.4 1.0 2.25 lsb full vi 1.75 2.5 2.75 lsb no missing codes 25c i guarant eed guaranteed guaranteed analog inputs voltage range minimum full vi 0.5 0.5 0.5 v p-p maximum full vi 1.0 1.0 1.0 v p-p gain tempco 25c v 135 150 150 ppm/c bias current 25c iv 1 1 1 a full iv 1 1 1 a full-scale matching full vi 8.0 8.0 8.0 % fs offset adjustment range full vi 43 48 53 43 48 53 43 48 53 % fs reference outputs voltage range full v 1.3 1.3 1.3 v temperature coefficient full v 90 90 90 ppm/c switching performance 1 max conversion rate full vi 100 140 170 msps min conversion rate full iv 10 10 10 msps clock-to-data skew, t skew full iv ?1.5 +2.5 ?1.5 +2.5 ?1.5 +2.5 ns serial port timing t buff full vi 4.7 4.7 4.7 s t stah full vi 4.0 4.0 4.0 s t dho full vi 250 250 250 ns t dal full vi 4.7 4.7 4.7 s t dah full vi 4.0 4.0 4.0 s t dsu full vi 100 100 100 ns t stasu full vi 4.7 4.7 4.7 s t stosu full vi 4.0 4.0 4.0 s hsync input frequency full iv 15 110 15 110 15 110 khz max pll clock rate full vi 100 140 170 mhz min pll clock rate full iv 12 12 12 mhz pll jitter 25c iv 500 700 2 440 650 3 370 500 4 ps p-p full iv 1000 2 700 3 700 4 ps p-p sampling phase tempco full iv 10 10 10 ps/c
ad9887a rev. b | page 4 of 52 ad9887aks-100 ad9887aks-140 ad9887aks-170 parameter temp test level min typ max min typ max min typ max unit digital inputs voltage high, v ih full vi 2.6 2.6 2.6 v voltage low, v il full vi 0.8 0.8 0.8 v current high, v ih full iv ?1.0 ?1.0 ?1.0 a current low, v il full iv 1.0 1.0 1.0 a capacitance 25c v 3 3 3 pf digital outputs voltage high, v oh full vi 2.4 2.4 2.4 v voltage low, v ol full vi 0.4 0.4 0.4 v duty cycle datack, datack full iv 45 55 60 45 55 60 45 55 65 % output coding binary binary binary power supplies v d supply voltage full iv 3.15 3.3 3.45 3.15 3.3 3.45 3.15 3.3 3.45 v v dd supply voltage full iv 2.2 3.3 3.45 2.2 3.3 3.45 2.2 3.3 3.45 v pv d supply voltage full iv 3.15 3.3 3.45 3.15 3.3 3.45 3.15 3.3 3.45 v i d supply current, v d 25c v 167 185 230 ma i dd supply current, v dd 5 25c v 33 46 55 ma ipv d supply current, pv d 25c v 43 43 60 ma total supply current 5 full vi 243 330 274 360 345 390 ma power-down supply current full vi 90 120 90 120 90 120 ma dynamic performance analog bandwidth, full power 25c v 330 330 330 mhz transient response 25c v 2 2 2 ns overvoltage recovery time 25c v 1.5 1.5 1.5 ns signal-to-noise ratio (snr) 6 25c v 46 46 45 db f in = 40.7 mhz crosstalk full v 60 60 60 dbc thermal characteristics ja junction-to-ambient thermal resistance 7 v 37 37 37 c/w 1 drive strength = 11. 2 vco range = 01, charge-pump current = 001, pll divider = 1693. 3 vco range = 10, charge-pump current = 110, pll divider = 1600. 4 vco range = 11, charge-pump current = 110, pll divider = 2159. 5 demux = 1, datack and datack load = 10 pf, data load = 5 pf. 6 using external pixel clock. 7 simulated typical performance with pa ckage mounted to a 4-layer board.
ad9887a rev. b | page 5 of 52 digital interface vd = 3.3 v, vdd = 3.3 v, clock = maximum, unless otherwise noted. table 2. ad9887aks parameter conditions temp test level min typ max unit resolution 8 bits dc digital i/o specifications high level input voltage, v ih full vi 2.6 v low level input voltage, v il full vi 0.8 high level output voltage, v oh full vi 2.4 v low level output voltage, v ol full vi 0.4 v input clamp voltage, v cinl i cl = ?18 ma iv gnd ? 0.8 v input clamp voltage, v cipl i cl = +18 ma iv v dd + 0.8 v output clamp voltage, v conl i cl = ?18 ma iv gnd ? 0.8 v output clamp voltage, v copl i cl = +18 ma iv v dd + 0.8 v output leakage current, i ol high impedance full iv ?10 +10 a dc specifications output high drive, i ohd (v out = v oh ) output drive = high full iv 13 ma output drive = med full iv 8 ma output drive = low full iv 5 ma output low drive, i old (v out = v ol ) output drive = high full iv ?9 ma output drive = med full iv ?7 ma output drive = low full iv ?5 ma datack high drive, i ohc (v out = v oh ) output drive = high full iv 25 ma output drive = med full iv 12 ma output drive = low full iv 8 ma datack low drive, i olc (v out = v ol ) output drive = high full iv ?25 ma output drive = med full iv ?19 ma output drive = low full iv ?8 ma differential input voltage, single-ended amplitude full iv 75 800 ma power supplies v d supply voltage full iv 3.15 3.3 3.45 v v dd supply voltage minimum value for two pixels per clock mode full iv 2.2 3.3 3.45 v pv d supply voltage full iv 3.15 3.3 3.45 v i d supply current 1 25c v 350 ma i dd supply current 1 , 2 255c v 40 ma ipv d supply current 1 255c iv 130 ma total supply current with hdcp 1 , 2 vi 520 560 ma ac specifications intrapair (+ to ?) differential input skew, t dps full iv 360 ps channel-to-channel differential input skew, t ccs full iv 1.0 clock period low-to-high transition time for data and controls, d lht output drive = high; c l = 10 pf full iv 2.5 ns output drive = med; c l = 7 pf full iv 3.1 ns output drive = low; c l = 5 pf full iv 5.4 ns
ad9887a rev. b | page 6 of 52 ad9887aks parameter conditions temp test level min typ max unit low-to-high transition time (d lht ) for datack output drive = high; c l = 10 pf full iv 1.2 ns output drive = med; c l = 7 pf full iv 1.6 ns output drive = low; c l = 5 pf full iv 2.3 ns high-to-low transition time (d hlt ) for data output drive = high; c l = 10 pf full iv 2.6 ns output drive = med; c l = 7 pf full iv 3.0 ns output drive = low; c l = 5 pf full iv 3.7 ns high-to-low transition time (d hlt ) for datack output drive = high; c l =10 pf full iv 1.4 ns output drive = med; c l = 7 pf full iv 1.6 ns output drive = low; c l = 5 pf full iv 2.4 ns clock-to-data skew, t skew 3 full iv 0 4.0 ns duty cycle, datack, datack 3 full iv 45 55 % of period high datack frequency (f cip ) 1 pixel/clock full vi 20 140 mhz datack frequency (f cip ) 2 pixels/clock full iv 10 85 mhz 1 the typical pattern contains a gray- scale area, output drive = high. 2 datack and datack load = 10 pf, data load = 5 pf, and hdcp disabled. 3 drive strength = 11.
ad9887a rev. b | page 7 of 52 absolute maximum ratings table 3. parameter rating v d 3.6 v v dd 3.6 v analog inputs v d to 0.0 v vrefin v d to 0.0 v digital inputs 5 v to 0.0 v digital output current 20 ma operating temperature range ?25c to +85c storage temperature range ?65c to +150c maximum junction temperature 150c maximum case temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. explanation of test levels i. 100% production tested. ii. 100% production tested at 25c; sample tested at specified temperatures. iii. sample tested only. iv. guaranteed by design and characterization testing. v. parameter is a typical value only. vi. 100% production tested at 25c; guaranteed by design and characterization testing. esd caution
ad9887a rev. b | page 8 of 52 pin configuration and fu nction descriptions 02838-002 nc = no connect gnd green a<7> green a<6> green a<3> green a<4> green a<5> v dd green a<2> green a<1> green a<0> gnd green b<7> green b<6> green b<5> green b<4> green b<3> green b<2> green b<1> green b<0> v dd gnd blue a<7> blue a<6> blue a<5> blue a<4> blue a<3> blue a<2> blue a<1> blue a<0> v dd v dd gnd blue b<7> blue b<6> blue b<5> blue b<4> blue b<3> blue b<2> blue b<1> blue b<0> 5 4 3 2 7 6 9 8 1 14 13 12 11 16 15 17 10 19 18 23 22 21 20 25 24 27 26 29 28 32 31 30 34 33 36 35 40 39 38 37 r ain r clamp v v d v d v d gnd r midsc v gnd gnd g midsc v g clamp v sogin v d gnd v d v d gnd gnd b midsc v b ain b clamp v v d gnd v d gnd ckinv clamp sda scl g ain a0 a1 pv d pv d gnd gnd coast ckext hsync vsync 116 117 118 119 114 115 112 113 120 107 108 109 110 105 106 104 111 102 103 98 99 100 101 96 97 94 95 92 93 89 90 91 87 88 85 86 81 82 83 84 51 52 53 54 55 56 57 58 59 60 41 42 43 44 45 46 47 48 49 50 61 62 63 64 66 67 68 69 70 65 71 72 73 74 76 77 78 79 75 80 gnd gnd v dd gnd scan out ctl0 ctl1 ctl2 mcl scan clk v d gnd rterm v d v d rx2+ rx2? gnd rx1+ rx1? gnd rx0+ rx0? gnd rxc+ rxc? v d v d gnd v d mda ddcsda ddcscl gnd pv d gnd pv d filt pv d gnd 150 149 148 147 146 145 144 143 142 141 160 159 158 157 156 155 154 153 152 151 140 139 138 137 135 134 133 132 131 136 130 129 128 127 125 124 123 122 126 121 red b<0> red b<1> red b<2> red b<3> red b<4> red b<5> red b<6> red b<7> gnd v dd red a<0> red a<1> red a<2> red a<3> red a<4> red a<5> red a<6> red a<7> gnd v dd sogout hsout vsout de s cdt datack gnd v dd gnd gnd scan in gnd v d refout refin v d v d gnd gnd ad9887a top view (not to scale) pin 1 identifier datack figure 2. pin configuration
ad9887a rev. b | page 9 of 52 table 4. pin function descriptions pin type mnemonic description value pin no. interface analog video data inputs r ain analog input for red channel 0.0 v to 1.0 v 119 analog g ain analog input for green channel 0.0 v to 1.0 v 110 analog b ain analog input for blue channel 0.0 v to 1.0 v 100 analog sync/clock inputs hsync horizontal sync input 3.3 v cmos 82 analog vsync vertical sync input 3.3 v cmos 81 analog sogin sync-on-green input 0.0 v to 1.0 v 108 analog clamp external clamp input (optional) 3.3 v cmos 93 analog coast pll coast signal input (optional) 3.3 v cmos 84 analog ckext external pixel clock input (to bypass the pll) to v dd or ground (optional) 3.3 v cmos 83 analog ckinv adc sampling clock invert (optional) 3.3 v cmos 94 analog sync outputs hsout horizontal sync output 3.3 v cmos 139 analog/digital vsout vertical sync output 3.3 v cmos 138 analog/digital sogout sync-on-green slicer output or raw hsync 3.3 v cmos 140 analog voltage references refout internal reference output (bypass with 0.1 f to ground) 1.25 v 126 analog refin reference input (1.25 v 10%) 1.25 v 10% 125 analog clamp voltages r midsc v red channel midscale clamp voltage output 0.5 v 50% 120 analog r clamp v red channel midscale clamp voltage input 0.0 v to 0.75 v 118 analog g midsc v green channel midscale clamp voltage output 0.5 v 50% 111 analog g clamp v green channel midscale clamp voltage input 0.0 v to 0.75 v 109 analog b midsc v blue channel midscale clamp voltage output 0.5 v 50% 101 analog b clamp v blue channel midscale clamp voltage input 0.0 v to 0.75 v 99 analog pll filter filt external filter connection (component of pll) 78 analog power supplies v d main power supply 3.3 v 5% 51, 54, 55, 67, 68, 70, 96, 98, 104, 105, 107, 114, 115, 117, 123, 124, 127 analog/digital v dd output power supply 3.3 v 5% 1, 11, 21, 31, 43, 132, 141, 151 analog/digital pv d pll power supply 3.3 v 5% 75, 77, 79, 87, 88 analog/digital gnd ground 0 v 2, 12, 22, 32, 41, 42, 44, 52, 58, 61, 64, 69, 74, 76, 80, 85, 86, 95, 97, 102, 103, 106, 112, 113, 116, 121, 122, 128, 130, 131, 133, 142, 152 analog/digital serial port sda serial port data i/o 3.3 v cmos 92 analog/digital
ad9887a rev. b | page 10 of 52 pin type mnemonic description value pin no. interface 2-wire serial interface scl serial port data clock (100 khz maximum) 3.3 v cmos 91 analog/digital a0 serial port address input 1 3.3 v cmos 90 analog/digital a1 serial port address input 2 3.3 v cmos 89 analog/digital data outputs red b[7:0] data output, red channel, port b/odd, bit 7 is the msb 3.3 v cmos 153 to 160 analog/digital green b[7:0] data output, green channel, port b/o dd 3.3 v cmos 13 to 20 analog/digital blue b[7:0] data output, blue, port b/ odd 3.3 v cmos 33 to 40 analog/digital red a[7:0] data output, red channel, port a/even 3.3 v cmos 143 to 150 analog/digital green a[7:0] data output, green channel, port a/ev en 3.3 v cmos 3 to 10 analog/digital blue a[7:0] data output, blue channel, port a/ev en 3.3 v cmos 23 to 30 analog/digital data clock outputs datack data outp ut clock 3.3 v cmos 134 analog/digital datack data output clock complement 3.3 v cmos 135 analog/digital sync detect s cdt sync detect output 3.3 v cmos 136 analog/digital scan function scan in input for scan function 3.3 v cmos 129 analog/digital scan out output for scan function 3.3 v cmos 45 analog/digital scan clk clock for scan function 3.3 v cmos 50 analog/digital digital video data inputs rx0+ digital differential input channel 0 true 62 digital rx0? digital differential input channel 0 complement 63 digital rx1+ digital differential input channel 1 true 59 digital rx1? digital differential input channel 1 complement 60 digital rx2+ digital differential input channel 2 true 56 digital rx2? digital differential input channel 2 complement 57 digital digital video clock inputs rxc+ digital differential data clock true 65 digital rxc? digital differential data clock complement 66 digital data enable de data enable 3.3 v cmos 137 digital control bit ctl0, ctl1, ctl2 digital control outputs 3.3 v cmos 46 to 48 digital termination control rterm internal termination resistance set pin 53 digital hdcp ddcscl hdcp slave serial port data clock 3.3 v cmos 73 digital ddcsda hdcp slave serial port data i/o 3.3 v cmos 72 digital mcl hdcp master serial port data clock 3.3 v cmos 49 digital mda hdcp master serial port data i/o 3.3 v cmos 71 digital
ad9887a rev. b | page 11 of 52 pin function detailspins shared between digital and analog interfaces sync outputs hsout horizontal sync output the horizontal sync output is a reconstructed version of the video hsync, phase-aligned with datack. the polarity of this output can be controlled via a serial bus bit. in analog interface mode, the placement and duration are variable. in digital interface mode, the placement and duration are set by the graphics transmitter. vsout vertical sync output the vsync is separated from a composite signal or a direct pass-through of the vsync input. the polarity of this output can be controlled via a serial bus bit. the placement and duration in all modes are set by the graphics transmitter. 2-wire serial port sda serial port data i/o scl serial port data clock a0 serial port address input 1 a1 serial port address input 2 for a full description of the 2-wire serial register and how it works, see the 2-wire serial control port section. data outputs red a data output, red channel, port a/even red b data output, red channel, port b/odd green a data output, green channel, port a/even green b data output, green channel, port b/odd blue a data output, blue channel, port a/even blue b data output, blue channel, port b/odd these outputs are the main data outputs. bit 7 is the msb. these outputs are shared between the two interfaces. data clock outputs datack data output clock datack data output clock complement like the data outputs, the data clock outputs are shared between the two interfaces. they also behave differently, depending on which interface is active. see the theory of operation and design guide analog interface and the theory of operation digital interface sections for details on how these pins behave. sync detect s cdt chip active/inactive detect output the logic for the s cdt pin is analog interface hsync detection or digital interface de detection. therefore, the s cdt pin switches to logic low under two conditions: when neither interface is active, or when the chip is in full power-down mode. the data outputs are automatically set to three-state when s cdt is low. this pin can be read by a controller to identify periods of inactivity. scan function scan in data input for scan function by using the scan function, 48 bits of data can be loaded into the data outputs. data is input serially through this pin, clocked with the scan clk pin, and comes through the outputs as parallel words. this function is useful for loading known data into a graphics controller chip for testing purposes. scan out data output for scan function the data input serially into the scan in register can be read through this pin. data is read on a fifo basis and is clocked via the scan clk pin. scan clk data clock for scan function this pin clocks the data for the scan function. it controls both data input and output.
ad9887a rev. b | page 12 of 52 power supplies v d main power supply these pins supply power to the main elements of the circuit. they should be filtered to be as quiet as possible. v dd digital output power supply these supply pins are identified separately from the v d pins; therefore, special care can be taken to minimize output noise transferred into the sensitive analog circuitry. if the ad9887a is interfacing with lower voltage logic, v dd can be connected to a lower supply voltage (as low as 2.2 v) for compatibility. pv d clock generator power supply the most sensitive portion of the ad9887a is the clock generation circuitry. these pins provide power to the clock pll and help the user design for optimal performance. the designer should provide noise-free power to these pins. gnd ground this is the ground return for all circuitry on the chip. it is recommended that the application circuit board have a single, solid ground plane.
ad9887a rev. b | page 13 of 52 pin function detailsanalog interface analog video data inputs r ain analog input for red channel g ain analog input for green channel b ain analog input for blue channel these are the high impedance inputs that accept graphics signals from the red, green, and blue channels, respectively. for rgb, the three channels are identical and can be used for any color, but colors are assigned for convenient reference. for proper 4:2:2 formatting in a yuv application, the y channel must be connected to the g ain input, u must be connected to the b ain input, and v must be connected to the r ain input. these pins accommodate input signals ranging from 0.5 v to 1.0 v full scale. signals should be ac-coupled to these pins to support clamp operation. external inputs hsync horizontal sync input this input receives a logic signal that establishes the horizontal timing reference and provides the fre- quency reference for pixel clock generation. the logic sense of this pin is controlled by serial register 0x0f, bit 7 (hsync polarity). only the leading edge of hsync is active; the trailing edge is ignored. when hsync polarity = 0, the falling edge of hsync is used. when hsync polarity = 1, the rising edge is active. the input includes a schmitt trigger for noise immunity with a nominal input threshold of 1.5 v. electrostatic discharge (esd) protection diodes conduct heavily if this pin is driven more than 0.5 v above the maximum tolerance voltage (3.3 v) or more than 0.5 v below ground. vsync vertical sync input this is the input for vertical sync. sync/clock inputs sogin sync-on-green input this input is provided to assist with processing signals with embedded sync, typically on the green channel. the pin is connected to a high speed com- parator with an internally generated threshold that is 0.15 v above the negative peak of the input signal. when connected to an ac-coupled graphics signal with embedded sync, it produces a noninverting digital output on sogout. when not used, leave this input unconnected. for more details on this function and how it should be configured, refer to the sync-on-green input section. clamp external clamp input (optional) this logic input can be used to define the time during which the input signal is clamped to the reference dc level (ground for rgb, midscale for yuv). it should be used when the reference dc level is known to be present on the analog input channels, typically during a period called the back porch of the graphics signal following hsync. the clamp pin is enabled by setting control bit extclmp to 1 (the default at power-up is 0). when disabled, this pin is ignored and the clamp timing is determined internally by counting the delay and duration from the trailing edge of the hsync input. the logic sense of this pin is controlled by clampol. when not used, this pin must be grounded and extclmp must be programmed to 0. coast clock generator coast input (optional) this input can be used to stop the pixel clock generator from synchronizing with hsync while maintaining the clock at its current frequency and phase. this is useful when processing signals from sources that fail to produce horizontal sync pulses when in the vertical interval. the coast signal is generally not required for pc-generated signals. for applications requiring coast, it is provided through the internal coast found in the sync processing engine. the logic sense of this pin is controlled by coast polarity. when not used, this pin can be grounded with coast polarity programmed to 1, or tied high with coast polarity programmed to 0. coast polarity defaults to 1 at power-up. ckext external clock input (optional) this pin can be used to provide an external clock to the ad9887a in place of the clock internally generated from hsync. it is enabled by program- ming ckext to 1. when an external clock is used, all other internal functions, including the clock phase adjustment, operate normally. when not used, this pin should be tied to v dd or to ground and ckext should be programmed to 0.
ad9887a rev. b | page 14 of 52 ckinv sampling clock inversion (optional) this pin can be used to invert the pixel sampling clock, which has the effect of shifting the sampling phase 180. this supports the alternate pixel sampling mode, wherein higher frequency input signals (up to 340 mpps) can be captured by sampling the odd pixels and capturing the even pixels on the subsequent frame. this pin should be used only during blanking intervals (typically vertical blanking), because it might produce several samples of corrupted data during the phase shift. ckinv should be grounded when not used. either or both signals can be used, depending on the timing mode and the interface design used. sync outputs hsout horizontal sync output a reconstructed, phase-aligned version of the hsync input. both the polarity and duration of this output can be programmed via serial bus registers. by maintaining alignment with datack, datack , and data, data timing with respect to horizontal sync can be determined. sogout sync-on-green slicer output this pin can be programmed to output either the composite sync output from the sync-on-green slicer comparator or an unprocessed, but delayed, version of the hsync input. see the sync processing block diagram ( figure 43 ) to see how this pin is connected. voltage references refout internal reference output this is the output from the internal 1.25 v band gap reference. this output is intended to drive relatively light loads. it can drive the ad9887a reference input directly, but should be externally buffered if it is used to drive other loads, as well. the absolute accuracy of this output is 4%, and the temperature coefficient is 50 ppm, which is adequate for most ad9887a applications. if higher accuracy is required, an external reference can be used instead. when using an external reference, connect this pin to ground through a 0.1 f capacitor. refin reference input the reference input accepts the master reference voltage for all ad9887a internal circuitry (1.25 v 10%). it can be driven directly by the refout pin. its high impedance presents a very light load to the reference source. this pin should always be bypassed to ground with a 0.1 f capacitor. pll filter filt external filter connection for proper operation, the pixel clock generator, pll, requires an external filter. connect the filter shown in figure 11 to this pin. for optimal performance, minimize noise and parasitics on this node. data outputs red a data output, red channel, port a/even red b data output, red channel, port b/odd green a data output, green channel, port a/even green b data output, green channel, port b/odd blue a data output, blue channel, port a/even blue b data output, blue channel, port b/odd these are the main data outputs. bit 7 is the msb. each channel has two ports. when the part is operated in single-channel mode (demux = 0), all data presented to port a and port b is placed in a high impedance state. programming demux to 1 establishes the dual-channel mode, wherein alternate pixels are presented to the port a and port b of each channel. these appear simultaneously; two pixels are presented at the time of every second input pixel when par is set to 1 (parallel mode). when par is set to 0, pixel data appears alternately on the two ports, one new sample with each incoming pixel (interleaved mode). in dual-channel mode, the first pixel after hsync is routed to port a. the second pixel goes to port b, the third to port a, and so on. the delay from pixel sampling time to output is fixed. when the sampling time is changed by adjusting the phase register, the output timing is shifted as well. the datack, datack , and hsout outputs are also moved; therefore, the timing relationship among the signals is maintained.
ad9887a rev. b | page 15 of 52 r midsc v red channel midscale clamp voltage output g midsc v green channel midscale clamp voltage output b midsc v blue channel midscale clamp voltage output r clamp v red channel midscale clamp voltage input g clamp v green channel midscale clamp voltage input b clamp v blue channel midscale clamp voltage input these pins are part of the circuit that provides a voltage reference for midscale clamping used in the capture of yuv and ypbpr input signals. these pins should be grounded through 0.1 f capacitors, as shown in figure 4 . data clock outputs datack data output clock datack data output clock complement these differential data clock output signals are used to strobe the output data and hsout into external logic. these signals are produced by the internal clock generator and are synchronous with the internal pixel sampling clock. when the ad9887a is operated in single-channel mode, the output frequency is equal to the pixel sampling frequency. when the ad9887a is operated in dual-channel mode, the clock frequency is half the pixel frequency. when the sampling time is changed by adjusting the phase register, the output timing is shifted as well. the data, datack, datack , and hsout outputs are moved; therefore, the timing relationship among the signals is maintained.
ad9887a rev. b | page 16 of 52 pin function detailsdigital interface digital video data inputs rx0+ digital differential input channel 0 true rx0? digital differential input channel 0 complement rx1+ digital differential input channel 1 true rx1? digital differential input channel 1 complement rx2+ digital differential input channel 2 true rx2? digital differential input channel 2 complement these pins receive three pairs of differential, low voltage, swing input pixel data from a digital graphics transmitter. digital video clock inputs rxc+ digital differential data clock true rxc? digital differential data clock complement these pins receive the differential, low voltage, swing input pixel clock from a digital graphics transmitter. termination control r term internal termination set pin this pin is used to set the termination resistance for all digital interface high speed inputs. to set this pin, place a resistor of 10 times the desired input termi- nation resistance between this pin (pin 53) and the ground supply. typically, the value of this resistor should be 500 . data enable de data enable this pin outputs the state of data enable (de). the ad9887a decodes de from the incoming stream of data. the de signal is high during active video and low when there is no active video. hdcp ddcscl hdcp slave serial port data clock for use in communicating with the hdcp-enabled dvi transmitter. ddcsda hdcp slave serial port data i/o for use in communicating with the hdcp-enabled dvi transmitter. mcl hdcp master serial port data clock connects the eeprom for reading the encrypted hdcp keys. mda hdcp master serial port data i/o connects the eeprom for reading the encrypted hdcp keys. ctl digital control outputs these pins output the control signals for the red and green channels. ctl0 and ctl1 correspond to the red channel input, and ctl2 and ctl3 correspond to the green channel input.
ad9887a rev. b | page 17 of 52 theory of operation and design guideanalog interface general description the ad9887a is a fully integrated solution for capturing analog rgb signals and digitizing them for display on flat panel monitors or projectors. the device is ideal for implementing a computer interface in hdtv monitors or for serving as the front end to high performance video scan converters. implemented in a high performance cmos process, the interface can capture signals with pixel rates of up to 170 mhz, or of up to 340 mhz with an alternate pixel sampling mode. the ad9887a includes all necessary input buffering, signal dc restoration (clamping), offset and gain (brightness and contrast) adjustment, pixel clock generation, sampling phase control, and output data formatting. all controls are programmable via a 2-wire serial interface. full integration of these sensitive analog functions makes system design straightforward and less sensitive to the physical and electrical environment. with an operating temperature range of 0c to 70c, the device requires no special environmental considerations. input signal handling the ad9887a has three high impedance analog input pins for the red, green, and blue channels that accommodate signals ranging from 0.5 v to 1.0 v p-p. signals are typically brought onto the interface board via a dvi-i connector, a 15-lead d connector, or bnc connectors. the ad9887a should be located as close as is practical to the input connector. signals should be routed via matched-impedance traces (normally 75 ) to the ic input pins. at this point, the signal should be resistively terminated (75 to the signal ground return) and capacitively coupled to the ad9887a inputs through 47 nf capacitors. these capacitors form part of the dc-restoration circuit (see figure 3 ). in an ideal world of perfectly matched impedances, the best performance would be obtained with the widest possible signal bandwidth. the wide bandwidth inputs of the ad9887a (330 mhz) would track the input signal continuously as it moves from one pixel level to the next and would digitize the pixel during a long, flat pixel time. in many systems, however, there are mismatches, reflections, and noise that result in excessive ringing and distortion of the input waveform. this makes it difficult to establish a sampling phase that provides good image quality. a small inductor in series with the input can be effective in rolling off the input bandwidth slightly and providing a high quality signal over a wider range of conditions. using a fair-rite #2508051217z0 high speed signal chip bead inductor in the circuit of figure 3 provides good results in most applications. 02838-003 rgb input r ain g ain b ain 47nf 75 figure 3. analog input interface circuit hsync and vsync inputs the ad9887a receives a horizontal sync signal and uses it to generate the pixel clock and clamp timing. it is possible to operate the ad9887a without applying hsync (using an external clock), but several of the chips features are unavailable. therefore, it is recommended to provide hsync. it can be in the form of either a sync signal directly from the graphics source or a preprocessed ttl- or cmos-level signal. the hsync input includes a schmitt-trigger buffer and is capable of handling signals that have long rise times with superior noise immunity. in typical pc-based graphics systems, the sync signals are simply ttl-level drivers feeding unshielded wires in the monitor cable. as such, no termination is required or desired. when the vsync input is selected as the source for vsync, it is used for coast generation and passed through to the vsout pin. serial control port the serial control ports are designed for 3.3 v logic. if there are 5 v drivers on the bus, the serial control port pins should be protected with 150 series resistors placed between the pull-up resistors and the input pins. output signal handling the digital outputs are designed and specified to operate from a 3.3 v power supply (v dd ), but can operate with a v dd as low as 2.5 v for compatibility with 2.5 v logic. clamping rgb clamping to digitize the incoming signal properly, adjust the dc offset of the input to fit the range of the on-board adcs. most graphics systems produce rgb signals with black at ground and white at approximately 0.75 v. however, if sync signals are embedded in the graphics, the sync tip is often at ground, the black level is at 300 mv, and the white level is at approximately 1.0 v. some common rgb line amplifier boxes use emitter-follower buffers to split signals and increase drive capability. this introduces a 700 mv dc offset to the signal. clamping removes this offset to allow proper capture.
ad9887a rev. b | page 18 of 52 the key to clamping is to identify a time when the graphics system is known to be producing a black signal. originating from crt displays, the electron beam is blanked by sending a black level during horizontal retrace to prevent disturbing the image. most graphics systems maintain this format of sending a black level between active video lines. an offset is then introduced that results in the adcs producing a black output (code 0x00) when the known black input is present. the offset remains in place when other signal levels are processed, and the entire signal is shifted to eliminate offset errors. in systems with embedded sync, a blacker-than-black signal (hsync) is produced briefly to signal the crt that it is time to begin a retrace. for obvious reasons, it is important to avoid clamping on the tip of hsync. fortunately, there is virtually always a period following hsync, called the back porch, when a good black reference is provided. this is the time when clamping should be done. the clamp timing can be established by using the clamp pin at the appropriate time (with extclmp = 1). the polarity of this signal is set by the clamp polarity bit. an easier method of clamp timing uses the ad9887a internal clamp timing generator. the clamp placement register is programmed with the number of pixel clocks that should pass after the trailing edge of hsync before clamping starts. a second register (clamp duration) sets the duration of the clamp. these are both 8-bit values, providing considerable flexibility in clamp generation. the clamp timing is referenced to the trailing edge of hsync, and the back porch (black reference) always follows hsync. to establish clamping, set the clamp placement to 0x08 (to provide eight pixel periods for the graphics signal to stabilize after sync) and set the clamp duration to 0x14 (to allow the clamp 20 pixel periods to re-establish the black reference). the value of the external input coupling capacitor affects the performance of the clamp. if the value is too small, there is an amplitude change during a horizontal line time (between clamping intervals). if the capacitor is too large, it takes an excessively long time for the clamp to recover from a large change in incoming signal offset. the recommended value (47 nf) results in recovery from a step error of 100 mv to within ? lsb in 10 lines, using a clamp duration of 20 pixel periods on a 60 hz sxga signal. yuv clamping yuv signals are slightly different from rgb signals in that the dc-reference level (black level in rgb signals) is at the midpoint of the u and v video signals. for these signals, it may be necessary to clamp to the midscale range of the adc range (0x80), rather than to the bottom of the adc range (0x00). clamping to midscale, rather than to ground, can be accomplished by setting the clamp select bits in the serial bus register. each of the three converters has its own selection bit so that it can be clamped to either midscale or ground independently. these bits (bit 0 to bit 2) are located in register 0x0f. the midscale reference voltage that each adc clamps to is independently provided on the r midsc v, g midsc v, a n d b midsc v pins. each converter must have its own midscale reference, because both offset adjustment and gain adjustment for each converter affect the dc level of midscale. during clamping, the y and v converters are clamped to their respective midscale reference inputs. these inputs are pin b clamp v and pin r clamp v for the u and v converters, respectively. the typical connections for both rgb and yuv clamping are shown in figure 4 . note that even if midscale clamping is not required, all midscale voltage outputs should be connected to ground through a 0.1 f capacitor. r midsc v r clamp v g midsc v g clamp v b midsc v b clamp v 0.1 f 0.1 f 0 .1 f 02838-044 figure 4. typical clamp configuration for rgb and yuv applications gain and offset control a block diagram of the gain and offset control integrated with each adc is shown in figure 5 . the ad9887a can accommodate input signals of 0.5 v to 1.0 v full scale. the full-scale range is set in three 8-bit registers (red gain, green gain, and blue gain). code 0 gives the minimum input range (a maximum of 0.5 v); code 255 corresponds to the maximum input range (a minimum of 1.0 v). increasing the gain setting results in an image with less contrast. the offset control shifts the entire input range, resulting in a change in image brightness. three 7-bit registers (red offset, green offset, and blue offset) provide independent settings for each channel. the offset controls provide a 63 lsb adjustment range. this range is connected with the full-scale range; therefore, if the input range is doubled (from 0.5 v to 1.0 v), the offset step size is also doubled (from 2 mv per step to 4 mv per step). figure 6 and figure 7 illustrate the interaction of gain and offset controls. the magnitude of an lsb in offset adjustment is propor- tional to the full-scale range, which is controlled by the gain setting. therefore, changing the full-scale range changes the offset (see figure 6 ). the change is minimal if the offset setting is near midscale. when changing the offset, the full-scale range is not affected, but the full-scale level is shifted by the same amount as the zero-scale level.
ad9887a rev. b | page 19 of 52 adc dac dac offset ref x1.2 in clamp v off 02838-010 7 gain 8 8 figure 5. adc block diagram (single-channel output) 02838-005 gain 0xff 0x00 input range (v) 1.0 0.5 0 offset = 0x00 offset = 0x3f offset = 0x7f offset = 0x00 offset = 0x7f offset = 0x3f figure 6. gain and offset control 1v input range v off (128 codes) input range 0.5v v off (128 codes) offset range 0v 0v offset range 02838-011 figure 7. relationship of offset range to input range sync-on-green input the sync-on-green input operates in two steps. first, with the aid of a negative peak detector, it sets a baseline clamp level from the incoming video signal. second, it sets the sync trigger level (nominally 150 mv above the negative peak). the exact trigger level is variable and can be programmed via register 0x11. the sync-on-green input must be ac-coupled to the green analog input through its own capacitor, as shown in figure 8 . the value of the capacitor must be 1 nf 20%. if sync-on-green is not used, this connection is not required and sogin should be left unconnected. (note that the sync-on-green signal is always negative polarity.) see the theory of operationsync processing section for more information. 02838-006 g ain sogin 1nf r ain 47nf b ain 47nf 47nf figure 8. typical clamp configuration for rgb and yuv applications clock generation a phase-locked loop (pll) is used to generate the pixel clock. the hsync input provides a reference frequency for the pll. a voltage-controlled oscillator (vco) generates a much higher pixel clock frequency. this is divided by the pll divide value (msbs in register 0x01 and lsbs in register 0x02) and phase compared with the hsync input. any error is used to shift the vco frequency and maintain lock between the two signals. the stability of this clock is important for providing the clearest, most stable image. during each pixel time, there is a period when the signal slews from the old pixel amplitude and settles at its new value. then, the input voltage is stable until the signal slews to a new value (see figure 9 ). the ratio of the slewing time to the stable time is a function of the bandwidth of the graphics dac, the bandwidth of the transmission system (cable and termination), and the overall pixel rate. clearly, if the dynamic characteristics of the system remain fixed, the slewing and settling times are likewise fixed. subtract these times from the total pixel period to determine the stable period. at higher pixel frequencies, both the total cycle time and stable pixel time are shorter. 02838-007 pixel clock invalid sample times figure 9. pixel sampling times
ad9887a rev. b | page 20 of 52 02838-008 pixel clock (mhz) 25.1 31.5 36.0 40.0 50.0 58.2 65.0 75.0 78.7 85.5 94.5 108.0 135.0 158.0 162.0 176.0 jitter (%) 6 5 4 3 2 1 0 ? the 2-bit vco range register. to lower the sensitivity of the output frequency to noise on the control signal, the vco operating frequency range is divided into four overlapping regions. the vco range register sets this operating range. because there are only three possible regions, just 2 lsbs of the vco range register are used. the frequency ranges for the lowest and highest regions are shown in table 5 . table 5. vco frequency ranges pv1 pv0 pixel clock range (mhz) 0 0 12 to 37 0 1 37 to 74 1 0 74 to 140 1 1 140 to 170 figure 10. pixel clock jitter vs. frequency ? the 3-bit charge-pump current register. this register allows the current that drives the low-pass loop filter to be varied. the possible current values are listed in table 6 . any jitter in the clock reduces the precision with which the sampling time can be determined and, thus, must be subtracted from the stable pixel time. the ad9887a clock generation circuit is designed to minimize jitter to less than 6% of the total pixel time in all operating modes, making its effect on valid sampling time negligible (see figure 10 ). table 6. charge-pump current/control bits ip2 ip1 ip0 current (a) 0 0 0 50 0 0 1 100 0 1 0 150 0 1 1 250 1 0 0 350 1 0 1 500 1 1 0 750 1 1 1 1500 the pll characteristics are determined by the loop-filter design, the pll charge-pump current, and the vco range setting. the loop-filter design is illustrated in figure 11 . recommended settings of vco range and charge-pump current for vesa standard display modes are listed in table 7 . c p 0.0039 f c z 0.039 f r z 3.3k filt pv d 02838-009 ? the 5-bit phase adjust register. the phase of the generated sampling clock can be shifted to locate an optimum sampling point within a clock cycle. the phase- adjust register provides 32 phase-shift steps of 11.25 each. the hsync signal with an identical phase shift is available through the hsout pin. phase adjustment is operational even if the pixel clock is provided externally. the coast signal allows the pll to continue to run at the same frequency in the absence of the incoming hsync signal. this can be used during the vertical sync period or any other time that the hsync signal is unavailable. the polarity of the coast signal can be set through the coast polarity bit, and the polarity of the hsync signal can be set through the hsync polarity bit. if not using automatic polarity detection, set the hsync and coast polarity bits to match the polarity of their respective signals. figure 11. pll loop-filter detail the following programmable registers are provided to optimize the performance of the pll: ? the 12-bit divisor register. the input hsync frequencies range from 15 khz to 110 khz. the pll multiplies the frequency of the hsync signal, producing pixel clock frequencies in the range of 12 mhz to 170 mhz. the divisor register controls the exact multiplication factor. this register can be set to any value between 221 and 4095. (the divide ratio used is the programmed divide ratio plus one.)
ad9887a rev. b | page 21 of 52 table 7. recommended vco range and charge-pump current settings for standard display formats standard resolution refresh rate (hz) horizontal frequency (khz) pixel rate (mhz) vcornge current vga 640 480 60 31.5 25.175 00 011 72 37.7 31.500 00 100 75 3735 31.500 00 100 85 43.3 36.000 00 101 svga 800 600 56 35.1 36.000 00 101 60 3739 40.000 01 011 72 4831 50.000 01 011 75 46.9 49.500 01 011 85 53.7 56.250 01 100 xga 1024 768 60 48.4 65.000 01 101 70 56.5 75.000 10 011 75 60.0 78.750 10 011 80 64.0 85.500 10 011 85 68.3 94.500 10 100 sxga 1280 1024 60 64.0 108.000 10 100 75 80.0 135.000 10 101 85 91.1 157.500 11 101 uxga 1600 1200 60 75.0 162.000 10 101 tv 480i 60 15.75 13.51 00 001 480p 60 31.47 27 00 100 720p 60 45.0 74.250 10 011 1080i 60 33.75 74.250 10 010 1080p 60 33.75 148.5 11 011
ad9887a rev. b | page 22 of 52 alternate pixel sampling mode logic 1 input on ckinv (pin 94) inverts the nominal adc clock. ckinv can be switched between frames to implement the alternate pixel sampling mode. this allows higher effective image resolution to be achieved at lower pixel rates, but with lower frame rates. on one frame, even pixels are digitized. on the subsequent frame, odd pixels are sampled. by reconstructing the entire frame in the graphics controller, a complete image can be reconstructed. this is very similar to the interlacing process used in broadcast television systems, but the interlacing is vertical instead of horizontal. the frame data is presented to the display at the full desired refresh rate (usually 60 hz) so that no flicker artifacts are added. 02838-014 oeoeoeoeoeoe oeoeoeoeoeoe oeoeoeoeoeoe oeoeoeoeoeoe oeoeoeoeoeoe oeoeoeoeoeoe oeoeoeoeoeoe oeoeoeoeoeoe oeoeoeoeoeoe oeoeoeoeoeoe figure 12. odd and even pixels in a frame 02838-015 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 o1 figure 13. odd pixels from frame 1 02838-016 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 figure 14. even pixels from frame 2 02838-017 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 o1 e2 figure 15. combined frame output from graphics controller 02838-018 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 o3 e2 figure 16. subsequent frame from controller
ad9887a rev. b | page 23 of 52 timinganalog interface three things happen to hsync in the ad9887a. first, the polarity of the hsync input is determined and, thus, has a known output polarity. the known output polarity can be programmed either active high or active low (register 0x04, bit 4). second, hsout is aligned with datack and data outputs. third, the duration of hsout (in pixel clocks) is set via register 0x07. use the hsout signal to drive the rest of the display system. the timing diagrams ( figure 18 through figure 27 ) show the operation of the ad9887a analog interface in all clock modes. the part establishes timing by sending the pixel corresponding with the leading edge of hsync to data port a. in dual-channel mode, the next sample is sent to data port b. subsequent samples are alternated between the a and b data ports. in single-channel mode, data is only sent to data port a, and data port b is placed in a high impedance state. coast timing in most computer systems, the hsync signal is provided continuously on a dedicated wire. in these systems, the coast input and function are unnecessary and should not be used. in some systems, however, hsync is disturbed during the vertical sync (vsync) period, and sometimes hsync pulses disappear. in other systems, such as those that use composite sync (csync) signals or those that embed sync-on-green (sog), hsync includes equalization pulses or other distortions during vsync. to avoid upsetting the clock generator during vsync, it is important to ignore these distortions. if the pixel clock pll sees extraneous pulses, it attempts to lock on to this new frequency and changes frequency by the end of the vsync period. it then requires a few lines of correct hsync timing to recover at the beginning of a new frame, resulting in a tearing of the image at the top of the display. the output data clock signal is created so that its rising edge always occurs between transitions of data port a and can be used to latch the output data externally. pxck any output signal datack (output) t skew t dcycle t per data out 0 2838-019 figure 17. analog output timing hsync timing horizontal sync is processed in the ad9887a to eliminate ambiguity in the timing of the le ading edge with respect to the phase-delayed pixel clock and data. the coast input is provided to eliminate this problem. it is an asynchronous input that disables the pll input and holds the clock at its current frequency. the pll can operate in this manner for several lines without significant frequency drift. the hsync input is used as a reference to generate the pixel sampling clock. the sampling phase can be adjusted with respect to hsync through a full 360 in 32 steps via the phase adjust register to optimize the pixel sampling time. display systems use hsync to align memory and display write cycles; therefore, it is important to have a stable timing relationship between the hsync output (hsout) and data clock (datack). coast can be provided by the graphics controller, or it can be internally generated by the ad9887a sync processing engine. p0 p1 p2 p3 p4 p5 p6 p7 d1 d2 d3 d4 d5 d6 rgb in hsync pxck hs adcck datack d outa hsout 02838-020 7-pipe delay figure 18. single-channel mode (analog interface)
ad9887a rev. b | page 24 of 52 d0 d2 p0 p1 p2 p3 p4 p5 p6 p7 rgb in hsync pxck hs adcck datack d outa hsout d4 02838-021 7-pipe delay figure 19. single-channel mode, alternate pixel sampling (even pixels, analog interface) d1 d3 d5 p0 p1 p2 p3 p4 p5 p6 p7 rgb in hsync pxck hs adcck datack d outa hsout d7 02838-022 7-pipe delay figure 20. single-channel mode, alternate pixel sampling (odd pixels, analog interface) p0 p1 p2 p3 p4 p5 p6 p7 d4 d0 d2 d1 d3 d5 rgb in hsync pxck hs adcck datack d outa hsout d outb 02838-023 7-pipe delay figure 21. dual-channel mode , interleaved outputs (analo g interface), outphase = 0
ad9887a rev. b | page 25 of 52 p0 p1 p2 p3 p4 p5 p6 p7 d0 d2 d4 rgb in hsync pxck hs adcck datack d outa hsout d outb d1 d3 d5 02838-024 8-pipe delay figure 22. dual-channel mode, parallel outputs (analog interface), outphase = 0 p0 p1 p2 p3 p4 p5 p6 p7 d4 d2 d6 rgb in hsync pxck hs adcck datack d outa hsout d outb d0 02838-025 7-pipe delay figure 23. dual-channel mode, interleaved outputs, alternate pixel sampling (even pixels, analog interface), outphase = 0 d1 d5 d3 p0 p1 p2 p3 p4 p5 p6 p7 rgb in hsync pxck hs adcck datack d outa hsout d outb d7 02838-026 8-pipe delay figure 24. dual-channel mode, interleaved outputs, alternate pixel sampling (odd pixels, analog interface), outphase = 0
ad9887a rev. b | page 26 of 52 pxck datack 7-pipe delay p0 p1 p2 p3 p4 p5 p6 p7 d0 d4 d2 d6 rgb in hsync hs adcck d outa d outb hsout 02838-027 figure 25. dual-channel mode, parallel outputs, alternate pixe l sampling (even pixels, analog interface), outphase = 0 p0 p1 p2 p3 p4 p5 p6 p7 d1 d5 d3 d7 rgb in hsync pxck hs adcck datack d outa d outb hsout 02838-028 8.5-pipe delay figure 26. dual-channel mode, parallel outputs, alternate pi xel sampling (odd pixels, analog interface), outphase = 0 p0 p1 p2 p3 p4 p5 p6 p7 u0 v2 u4 v4 rgb in hsync pxck hs adcck datac k r outa hsout y0 y1 y2 y3 y4 y5 g outa v0 u2 02838-029 7-pipe delay figure 27. 4:2:2 output mode
ad9887a rev. b | page 27 of 52 theory of operationinterface detection active interface detection and selection for interface detection in the ad9887a, the system should determine the correct interface and set the chip appropriately through the serial bus. an external circuit should be used to determine if the digital interface is active. a typical schematic for this detection function is shown in figure 28 . it is recommended that the system implement the interface selection criteria, as described in table 8 . because the digital interface clock detect bit (0x11[4]) has been unreliable in some applications, it is recommended that the active interface override bit (0x12[7]) be set to 1. this allows the system to select the interface through the serial bus register active interface select (ais) bit (0x12[6]). this selection should be based on the analog interface detect obtained by oring bit 7, bit 6, and bit 5 of register 0x11 and on the digital interface detect obtained through the external circuitry shown in figure 28 . when both interfaces are active, priority must be determined by the system and the appropriate interface must be selected via the ais bit. + ? 9 10 1 2 5 6 8 10k ? 10k ? 11k ? 10k ? 0.1f 0.1f clk+ clk? 1.0f 10k ? clk active 3.3 v 1 = dvi clock active 0 = dvi clock not active high speed comparator lt1715 02838-043 figure 28. external digital interface clock detect circuit hot-plug detect in some hdcp-enabled applications it may be desirable to be able to switch between the analog and dvi interfaces without having an dvi plug/unplug event. in these applications, the circuit in figure 29 should be used for the hot-plug detect connection. the fet switch should be controlled by the system-level software to force an hpd event whenever the selected interface is switched from the analog input to the dvi input. hpd +5v 14 15 hpd control bit 02838-046 1k? figure 29. manual hot-plug detect power management the ad9887a is a dual-interface device with shared outputs. because only one interface can be used at a time, the unused interface should be powered down. when the analog interface is being used, most of the digital interface circuitry can be powered down and vice versa. this helps to minimize the total power dissipation of the ad9887a. in addition, if neither interface has activity on it, both interfaces should be powered down. the correct power-down state is set by selecting an interface to be active through the serial bus when either or both interfaces are active, and by setting the power-down register bit (0x12[0]) to 0 when neither interface has activity on it. in a given power mode, not all circuitry in the inactive interface is powered down completely. when the digital interface is active, hsync detect circuitry is not powered down. sog, outputs, and the band gap reference are powered up if either interface is active. the serial bus stays active even if the entire chip is powered down. table 8. interface selection and power-down controls power- down active interface override (0x12[7]) analog interface detect (0x11[7], 0x11[6], or 0x11[5]) digital interface detect (from external circuit) ais active interface description 1 1 x x 0 analog force the analog interface active. 1 1 x x 1 digital force the digital interface active. 0 x 0 0 x none neither interface is detected. both interfaces are powered down and the s cdt pin is set to logic 0. 1 1 0 1 1 digital the digital interface is detected. power down the analog interface. 1 1 1 0 0 analog the analog interface is detected. power down the digital interface. 1 1 1 1 0 analog both interfaces are detected. the analog interface has priority. 1 1 1 1 1 digital both interfaces are detected. the digital interface has priority.
ad9887a rev. b | page 28 of 52 scan function the scan function is intended as a pseudo jtag function for the manufacturing test of the board. the ordinary operation of the ad9887a is disabled during scanning. to enable the scan function, set register 0x14, bit 2, to 1. to scan data to all 48 digital outputs, apply 48 serial bits of data and 48 clock cycles (typically 5 mhz, maximum of 20 mhz) to the scan in and scan clk pins, respectively. the data is shifted in upon the rising edge of scan clk . the first serial bit shifted in appears at the red a<7> output after one clock cycle. after the next clock cycle, the first bit is shifted to red a<6> and the next bit appears at red a<7>. after 48 clock cycles, the first bit is shifted to the blue b<0> output and the 48th bit appears at the red a<7> output. if scan clk continues after 48 cycles, the data continues to be shifted from red a<7> to blue b<0> and comes out of the scan out pin as serial data upon the falling edge of scan clk . this is illustrated in figure 30 . a setup time (t su ) of 3 ns should be more than adequate; no hold time (t hold ) is required (0 ns). this is illustrated in figure 31 . x bit 1 bit 2 x x x bit 1 bit 2 bit 47 bit 48 x bit 46 bit 47 bit 48 x scan clk red a<7> blue b<0> scan out scan in bit 1 bit 2 bit 3 bit 1 bit 2 bit 3 xxx x x x 02838-012 figure 30. scan timing scan clk scan in 02838-013 t su = 3ns t hold = 0ns figure 31. scan set-up and hold times
ad9887a rev. b | page 29 of 52 theory of operationdigital interface capturing encoded data the first step in recovering encoded data is to capture the raw data. to accomplish this, the ad9887a uses a high speed, phase-locked loop (pll) to generate clocks capable of oversampling the data at the correct frequencies. the data capture circuitry continuously monitors the incoming data during horizontal and vertical blanking periods (when de is low) and independently selects the best sampling phase for each data channel. the phase infor- mation is stored and used until the next blanking period (one video line). data frames the digital interface data is captured in groups, called data frames, of 10 bits each. during the active data period, each frame is made up of nine encoded video data bits and one dc- balancing bit. the data capture block receives this data serially, but outputs each frame in parallel, 10-bit words. special characters during periods of horizontal or vertical blanking (when de is low), the digital transmitter transmits special characters that are used to set the video frame boundaries and the phase recovery loop for each channel. there are four special characters that can be received. they are used to identify the top, bottom, left side, and right side of each video frame. the data receiver can differ- entiate these special characters from active data, because the special characters have a different number of transitions per data frame. channel resynchronization the purpose of the channel resynchronization block is to resynchronize the three data channels to a single internal data clock. even if all three data channels are on different phases of the pll clock (0, 120, and 240), this block can resynchronize the channels from a worst-case skew of one full input period (8.93 ns at 170 mhz). data decoder the data decoder receives frames of data and sync signals from the data capture block in 10-bit, parallel words and decodes them into groups of eight rgb/yuv bits, two control bits, and a data enable (de) bit. hdcp the ad9887a contains circuitry necessary for decrypting a high-bandwidth digital content protection (hdcp) encoded dvi video stream. a typical hdcp implementation is shown in figure 32 . several features of the ad9887a make decryption possible and ease the implementation of hdcp. the basic components of hdcp are included in the ad9887a. a slave serial bus connects to the ddc clock and the ddc data pins on the dvi connector to allow the hdcp-enabled dvi transmitter to coordinate the hdcp algorithm with the ad9887a. a second serial port (mda/mcl) allows the ad9887a to read the hdcp keys and key selection vector (ksv) stored in an external se rial eeprom. when transmitting encrypted video, the dvi transmitter enables hdcp through the ddc port. the ad9887a then decodes the dvi stream using information provided by the transmitter, hdcp keys, and ksv. the ad9887a allows the mda and mcl pins to be three-state, using the mda/mcl three-state bit (register 0x1b, bit 7) in the configuration registers. the three-state feature allows the eeprom to be programmed in-circuit. the mda/mcl port must be three-state before attempting to program the eeprom using an external master. the keys are stored in an i 2 c?-compatible 3.3 v serial eeprom of at least 512 bytes. the eeprom should have a device address of 0xa0. proprietary software licensed from analog devices, inc. encrypts the keys and creates properly formatted eeprom images for use in a production environment. encrypting the keys helps maintain the confidentiality of the hdcp keys, as required by the hdcp v1.0 specification. the ad9887a includes hardware for decrypting the keys in the external eeprom. adi provides a royalty-free license for the proprietary software needed by customers to encrypt the keys between the ad9887a and the eeprom only after customers provide evidence of a completed hdcp adopters license agreement and sign the analog devices software license agreement . the adopters license agreement is maintained by digital content protection, llc and can be downloaded from www.digital-cp.com . to obtain the analog devices software license agreement , contact the display electronics product line directly by sending an email to flatpanel_apps@analog.com .
ad9887a rev. b | page 30 of 52 scl sda eeprom ad9887a ddcscl mcl ddcsda mda ddc clock ddc data dvi-vcc ds ds 3.3v 3.3v 5k 5k pull-up resistors series resistor 150 3.3v 10k pull-up resistor 2k 2k pull-up resistors 3.3v dvi connector 02838-045 figure 32. hdcp implementation using the ad9887a
ad9887a rev. b | page 31 of 52 general timing diagramsdigital interface 80% 80% 20% 20% d lht d lht 02838-031 figure 33. digital output rise and fall times 02838-032 t cip , r cip t cil , r cil t cih , r cih figure 34. clock cycle/high/low times v diff = 0v v diff = 0v rx0 rx1 rx2 02838-033 t ccs figure 35. channel-to-channel skew timing datack (internal) datack (pin) t skew data out 02838-034 figure 36. dvi output timing timing mode diagra msdigital interface first pixel second pixel third pixel fourth pixel internal odclk datack de qe[23:0] qo[23:0] 02838-035 t st figure 37. one pixel per clock (datack inverted) first pixel second pixel third pixel fourth pixel datack de qe[23:0] qo[23:0] interna l odclk 02838-036 t st figure 38. one pixel per clock (datack not inverted) first pixel second pixel third pixel fourth pixel datack de qe[23:0] qo[23:0] internal odclk 02838-037 t st figure 39. two pixels per clock first pixel second pixel third pixel fourth pixel datack de qe[23:0] qo[23:0] internal odclk 02838-038 t st figure 40. two pixels per clock (datack inverted)
ad9887a rev. b | page 32 of 52 2-wire serial register map the ad9887a is initialized and controlled by a set of registers that determine the operating modes. an external controller is u sed to write and read the control registers through the 2-line serial interface port. table 9. control register map address read and write, or read only bits default value register name description 0x00 ro 7:0 chip revision bit 7 through bit 4 represent func tional revisions to the analog interface. bit 3 through bit 0 represent nonfunctional related revisions. revision 0 = 0000 0000. 0x01 r/w 7:0 01101001 pll divide ratio msbs this register is for bits[11:4] of the pll divider. larger values mean the pll operates at a faster rate. this register should be loaded first when a change is needed. (this gives the pll more time to lock.) 1 0x02 r/w 7:4 1101**** pll divide ratio lsbs this register is for bits[3:0] of th e pll divider. links to the pll divide ratio msbs to make a 12-bit value. 1 0x03 r/w 7:2 1******* clock generator controls bit 7must be set to 1 for proper device operation. *01***** bits[6:5]vco range select. selects vco frequency range (see the pll section). ***001** bits[4:2]charge-pump current. vari es the current that drives the low-pass filter (see the pll section). 0x04 r/w 7:3 10000*** clock phase adjust clock phase adjust. larger values mean more delay. (1 lsb = t/32) 0x05 r/w 7:0 10000000 clamp placement places the clamp signal an integer number of clock periods after the trailing edge of the hsync signal. 0x06 r/w 7:0 10000000 clamp duration number of clock peri ods that the clamp signal is actively clamping. 0x07 r/w 7:0 00100000 hsync output pulse width sets the number of pixel clocks that hsout remains active. 0x08 r/w 7:0 10000000 redgain controls adc input range (contrast) of red channel. bigger values result in less contrast. 0x09 r/w 7:0 10000000 greengain controls adc input range (contrast) of green channel. bigger values result in less contrast. 0x0a r/w 7:0 10000000 bluegain controls adc input range (contrast) of blue channel. bigger values result in less contrast. 0x0b r/w 7:1 1000000* redofst controls dc offset (brightness) of red channel. bigger values decrease brightness. 0x0c r/w 7:1 1000000* greenofst controls dc offset (brightness) of green channel. bigger values decrease brightness. 0x0d r/w 7:1 1000000* blueofst controls dc offset (brightness) of blue channel. bigger values decrease brightness. 0x0e r/w 7:3 1******* mode control 1 bit 7channel mode. determines single-channel or dual-channel output mode. logic 0 = single-channel mode; logic 1 = dual-channel mode. *1****** bit 6output mode. determines interl eaved or parallel output mode. logic 0 = interleaved mode; logic 1 = parallel mode. **0***** bit 5output port phase (outphase) . determines whic h port outputs the first data byte after hsync. logic 0 = b port; logic 1 = a port. ***0**** bit 4hsync output polarity. logic 0 = logic high sync; logic 1 = logic low sync. ****0*** bit 3vsync output invert. logic 0 = invert; logic 1 = no invert. 0x0f r/w 7:0 1******* pll and clamp control bit 7hsync input polarity. indicates the polarity of incoming hsync signal to the pll. logic 0 = active low; logic 1 = active high. *1****** bit 6coast input polarity. changes polarity of external coast signal. logic 0 = active low; logic 1 = active high. **0***** bit 5clamp input signal source (extclmp). chooses between hsync for clamp signal and another external signal to be used for clamping. logic 0 = hsync; logic 1 = externally provided clamp signal.
ad9887a rev. b | page 33 of 52 address read and write, or read only bits default value register name description ***1**** bit 4clamp input signal polarity (name also same as bit 6). valid only with external clamp signal. logic 0 = active low; logic 1 = active high. ****0*** bit 3external clock select (extcl k). shuts down the pll and allows the use of an external clock to drive the part. logic 0 = uses internal pll; logic 1 = bypasses the internal pll. *****0** bit 2red clamp select. logic 0 selects clamp to ground; logic 1 selects clamp to midscale. (voltage at pin 120 and 118) ******0* bit 1green clamp select. logic 0 selects clamp to ground; logic 1 selects clamp to midscale. (voltage at pin 111 and 109) *******0 bit 0blue clamp select. logic 0 selects clamp to ground; logic 1 selects clamp to midscale. (voltage at pin 101 and 99) 0x10 r/w 7:2 0******* mode control 2 bit 7ckinv: data output clock invert. logic 0 = not inverted; logic 1 = inverted (digital interface only). *0****** bit 6pixel select. selects either one or two pixels per clock mode. logic 0 = one pixel/clock; logic 1 = two pixels/clock (digital interface only). **11**** bit 5, 4output drive. selects among high, medium, and low output drive strength. logic 11 or logic 10 = high, logic 01 = medium, and logic 00 = low. ****0*** bit 3pdo: high impedance outputs. logic 0 = normal; logic 1 = high impedance. *****1** bit 2sync detect polarity. this bit sets the polarity for the s cdt pin. logic 1 = active high; logic 0 = active low. 0x11 ro 7:1 1******* sync detection and active interface control bit 7analog interface hsync detect. it is set to logic 1 if hsync is present on the analog interface; otherwise, it is set to logic 0. *1****** bit 6analog interface sync-on-green detect. it is set to logic 1 if sync is present on the green video input; otherwise, it is set to 0. **1***** bit 5analog interface vsync detect. it is set to logic 1 if vsync is present on the analog interface; otherwise, it is set to logic 0. ***1**** bit 4digital interface clock detect. it is set to logic 1 if the clock is present on the digital interface; otherwise, it is set to logic 0. ****1*** bit 3active interface (ai). this bit indicates which interface is active. logic 0 = analog interface; logic 1 = digital interface. *****1** bit 2active hsync (ahs). this bit in dicates which analog hsync is being used. logic 0 = hsync input pin; logic 1 = hsync from sync-on-green. ******1* bit 1active vsync (avs). this bit in dicates which analog vsync is being used. logic 0 = vsync input pin; logic 1 = vsync from sync-on-green. 0x12 r/w 7:0 0******* active interface bit 7active interface override (aio). if set to logic 1, the user can select the active interface via bit 6. if set to logic 0, the active interface is selected via bit 3 in register 0x11. *0****** bit 6active interface select (ais). logic 0 selects the analog interface as active. logic 1 selects the digital interface as active. note that the indicated interface is active only if bit 7 is set to logic 1 or if both interfaces are active (bit 6 or bit 7 and bit 4 = logic 1 in register 0x11). **0***** bit 5active hsync override. if set to logic 1, the user can select the hsync to be used via bit 4. if set to logic 0, the active interface is selected via bit 2 in register 0x11. ***0**** bit 4active hsync select. logic 0 selects hsync as the active sync. logic 1 selects sync-on-green as the active sync. note that the indicated hsync is used only if bit 5 is set to logic 1 or if both syncs are active (bit 6 and bit 7 = logic 1 in register 0x11). ****0*** bit 3active vsync override. if set to logic 1, the user can select the vsync to be used via bit 2. if set to logic 0, the active interface is selected via bit 1 in register 0x11.
ad9887a rev. b | page 34 of 52 address read and write, or read only bits default value register name description *****0** bit 2output vsync select. logic 0 selects raw vsync as the output vsync. logic 1 selects sync separator output as the active vsync. note that the indicated vsync is used on ly if bit 3 is set to logic 1. ******0* bit 1coast select. logic 0 selects the coast input pin used for the pll coast. logic 1 selects vsync to be used for the pll coast. *******1 bit 0 pwrdn . full chip power-down, active low. logic 0 = full chip power-down; logic 1 = normal. 0x13 r/w 7:0 00100000 sync separator threshold sync separator threshold. sets the number of clock cycles that the sync separator counts before toggling high or low. this should be set to a number greater than the maximum hs ync or equalizati on pulse width. 0x14 r/w 7:0 ***1**** control bits bit 4must be set to 1 for proper operation. ****0*** bit 3must be set to 0 for proper operation. *****0** bit 2scan enable. logic 0 = scan function disabled; logic 1 = scan function enabled. ******0* bit 1coast input polarity override. logic 0 = polarity determined by chip; logic 1 = polarity determined by user via bit 6 in register 0x0f. *******0 bit 0hsync input polarity override. logic 0 = polarity determined by chip; logic 1 = polarity determined by user via bit 7 in register 0x0f. 0x15 ro 7:5 0******* polarity status bit 7hsync input polarity status. logic 0 = active low; logic 1 = active high. *0****** bit 6vsync output polarity status. logic 0 = active high; logic 1 = active low. **0***** bit 5coast input polarity status. logic 0 = active low; logic 1 = active high. 0x16 r/w 7:2 10111*** control bits bits[7:3]sync-on-green slicer threshold. *****1** bit 2must be set to 0 for proper operation. 0x17 r/w 7:0 00000000 precoast sets the number of hs yncs prior to vsync before which coast goes active. 0x18 r/w 7:0 00000000 postcoast sets the number of hsyncs following vsyn c before coast goes active. 0x19 r/w 7:0 00000000 test register must be set to default for proper operation. 0x1a r/w 7:0 11111111 test must be set to 01000001 for proper operation. 0x1b r/w 7:0 00000000 set to 0x00 for autogain mode and 0x10 for manual-gain mode 0x1c r/w 7:0 00000*** bits [7:3]set to 00000*** for autogain mode and 00101*** for manual-gain mode *****1** bit 2cbcr output order. ******1* bit 1must be set to 0 for standard input sampling. *******1 4:2:2 control bit 0output format mode select. logic 1 = 4:4:4 mode; logic 0 = 4:2:2 mode. 0x1d ro 7:0 *_***** hdcp keys detected. logic 0 = not detected; logic 1 = detected. 0x1e r/w 7:0 11111111 must set to 0xff for proper operation. 0x1f r/w 7:0 10000100 must set to 0x84 for proper operation. 0x20 r/w 7:0 0******* bit 7hdcp a0 serial address bit. for logic 0, address = 0x74. for logic 1, address = 0x76. *0****** bit 6mda pin select. for logic 0, pin 49 = ctrl3 signal. for logic 1, pin 49 = mda for hdcp. **0***** bit 5analog input bandwidth control. logic 0 = high. ***0**** bit 4mda/mcl three-state. logic 0 = three-state; logic 1 = normal operation. ****1*** bit 3external oscillator. logic 1 = internal; logic 0 = use external oscillator on a0. *****0** normal operation. 0x21 r/w 7:0 00000000 tdms gain control set to 0x00 for autogain mode and 0x64 for manual-gain mode.
ad9887a rev. b | page 35 of 52 address read and write, or read only bits default value register name description 0x22 r/w 7:0 00000000 must be set to default. 0x23 r/w 7:0 00000000 must be set to 0x2a for proper operation. 0x24 r/w 7:0 00000000 must be set to default. 0x25 r/w 7:0 11110000 must be set to default. 0x26 r/w 7:0 11111111 must be set to default. 0x27 00001111 must be set to default 1 the ad9887a only updates the p ll divide ratio when the lsbs are written to register 0x02. 2-wire serial control register details chip identification 0x00 7:0 chip revision bit 7 through bit 4 represent functional revisions to the analog interface. changes in these bits generally indicate that software and/or hardware changes are required for the chip to work properly. bit 3 through bit 0 represent nonfunctional related revisions and are reset to 0000 when the msbs are changed. changes in these bits are considered transparent to the user. pll divider control 0x01 7:0 pll divide ratio msbs the 8 msbs of the 12-bit pll divide ratio plldiv. (the operational divide ratio is plldiv 1.) the pll derives a pixel clock from the incoming hsync signal. the pixel clock frequency is then divided by an integer value, such that the output is phase-locked to hsync. this plldiv value determines the number of pixel times (pixels plus horiontal blanking overhead) per line. this is typically 20 to 30 more than the number of active pixels in the display. the 12-bit value of the pll divider supports divide ratios from 221 to 4095. the higher the value loaded in this register, the higher the resulting clock frequency with respect to a fixed hsync frequency. vesa has established standard timing specifications that help determine the value for plldiv as a function of horiontal and vertical display resolution and frame rate ( table 7 ). however, many com- puter systems do not conform precisely to the recom- mendations, and these numbers should be used only as a guide. the display system manufacturer should provide automatic or manual means for optimiing plldiv. an incorrectly set plldiv usually produces one or more vertical noise bars on the display. the greater the error, the greater the number of bars produced. the power-up default of plldiv is 1693 (plldivm 0x69, plldivl 0xdx). the ad9887a updates the full divide ratio only when the lsbs are changed. writing to this register by itself does not trigger an update. 0x02 7:4 pll divide ratio lsbs the 4 lsbs of the 12-bit pll divide ratio plldiv. the operational divide ratio is plldiv 1. the power-up default value of plldiv is 1693 (plldivm 0x69, plldivl 0xdx). the ad9887a updates the full divide ratio only when the user writes to this register. clock generator controls 0x03 7 test must be set to 1 for proper device operation. 0x03 6:5 vco range select two bits that establish the operating range of the clock generator. vcornge must be set to correspond with the desired operating frequency (incoming pixel rate). the pll provides the best jitter performance at high frequencies. to output low pixel rates while minimiing jitter, the pll operates at a higher frequency and divides down the clock rate afterwards. table 10 shows the pixel rates for each vco range sett ing. the pll output divisor is automatically selected with the vco range setting. table 10. vco ranges vcornge pixel rate range 00 12 to 37 01 37 to 74 10 74 to 140 11 140 to 170 the power-up default value is 01.
ad9887a rev. b | page 36 of 52 0x03 4C2 current charge-pump current three bits that establish the current driving the loop filter in the clock generator. table 11. charge-pump currents current current (a) 000 50 001 100 010 150 011 250 100 350 101 500 110 750 111 1500 see table 7 for the recommended current settings. the power-up default value is current = 001. 0x04 7:3 clock phase adjust a 5-bit value that adjusts the sampling phase in 32 steps across one pixel period. each step represents an 11.2 shift in sampling phase. the power-up default value is 16. clamp timing 0x05 7:0 clamp placement an 8-bit register that sets the position of the internally generated clamp. when extclmp = 0, a clamp signal is generated internally at a position established by the clamp placement for a duration set by the clamp duration. clamping is started [clamp placement] pixel periods after the trailing edge of hsync. the clamp placement can be programmed to any value between 1 and 255. a value of 0 is not supported. the clamp should be placed during a time when the input signal presents a stable black-level reference, usually during a period between hsync and the image called the back porch. when extclmp = 1, this register is ignored. 0x06 7:0 clamp duration an 8-bit register that sets the duration of the internally generated clamp. when extclmp = 0, a clamp signal is generated internally at a position established by the clamp placement for a duration set by the clamp duration. clamping is started [clamp placement] pixel periods after the trailing edge of hsync and continues for [clamp duration] pixel periods. the clamp duration can be programmed to a value between 1 and 255. a value of 0 is not supported. for the best results, the clamp duration should be set to include the majority of the black reference signal time that follows the hsync signal trailing edge. insufficient clamping time can produce brightness changes at the top of the screen and can cause slow recovery from large changes in the average picture level (apl) or brightness. when extclmp = 1, this register is ignored. hsync pulse width 0x07 7:0 hsync output pulse width an 8-bit register that sets the duration of the hsync output pulse. the leading edge of the hsync output is triggered by the internally generated, phase-adjusted pll feedback clock. the ad9887a counts the number of pixel clock cycles set in this register. this triggers the trailing edge of the hsync output, which is also phase adjusted. input gain 0x08 7:0 red channel gain adjust (redgain) an 8-bit word that sets the gain of the red channel. the ad9887a can accommodate input signals with a full-scale range between 0.5 v and 1.5 v p-p. setting redgain to 255 corresponds to an input range of 1.0 v. a redgain of 0 establishes an input range of 0.5 v. note that increasing redgain results in the picture having less contrast because the input signal uses fewer of the available converter codes (see figure 6 ). 0x09 7:0 green channel gain adjust (greengain) an 8-bit word that sets the gain of the green channel. see redgain (0x08). 0x0a 7:0 blue channel gain adjust (bluegain) an 8-bit word that sets the gain of the blue channel. see redgain (0x08). input offset 0x0b 7:1 red channel offset adjust (redofst) a 7-bit offset binary word that sets the dc offset of the red channel (redofst). an offset adjustment of 1 lsb equals approximately 1 lsb change in the adc offset. therefore, the absolute magnitude of the offset adjustment scales as the gain of the channel changes. a nominal setting of 63 results in the channel nominally clamping to code 00 during the back porch clamping interval. an offset setting of 127 results in the channel clamping to code 63 of the adc. an offset setting of 0 clamps to code ?63 (off the bottom of the range). increasing the value of red offset decreases the brightness of the channel.
ad9887a rev. b | page 37 of 52 0x0c 7:1 green channel offset adjust (greenofst) a 7-bit offset binary word that sets the dc offset of the green channel. see redofst (0b). 0x0d 7:1 blue channel offset adjust (blueofst) a 7-bit offset binary word that sets the dc offset of the blue channel. see redofst (0b). mode control 1 0x0e 7 channel mode a bit that determines whether all pixels are presented to a single port (port a), or if alternating pixels are demulti- plexed to port a and port b. table 12. channel mode settings demux function 0 all data goes to port a 1 alternate pixels go to port a and port b when demux = 0, port b outputs are in a high imped- ance state. the maximum data rate for single-port mode is 100 mhz. the timing diagrams show the effects of this option. the power-up default value is 1. 0x0e 6 output mode a bit that determines whether all pixels are simultaneously presented to port a and port b upon every second datack rising edge or alternately presented to port a and port b upon successive datack rising edges. table 13. output mode settings parallel function 0 data is interleaved 1 data is simultaneous u pon every other data clock when in single-port mode (demux = 0), this bit is ignored. the timing diagrams (figure 18 through figure 27 and figure 37 through figure 39) show the effects of this option. the power-up default value is parallel = 1. 0x0e 5 output port phase one bit that determines whether even or odd pixels go to port a. table 14. output port phase (outphase) settings outphase first pixel after hsync 1 port b 0 port a in normal operation (outphase = 0) when operating in dual-port output mode (demux = 1), the first sample after the hsync leading edge is presented to port a, every subsequent odd sample goes to port a, and all even samples go to port b. when outphase = 1, these ports are reversed and the first sample goes to port b. when demux = 0, this bit is ignored because data always comes out of only port a. 0x0e 4 hsync output polarity one bit that determines the polarity of the hsync output and the sog output. table 15 shows the effect of this option. sync indicates the logic state of the sync pulse. table 15. hsync output polarity settings setting hsync 0 logic 1 (negative polarity) 1 logic 0 (positive polarity) the default setting for this register is 1. this option works on both the analog and digital interfaces. 0x0e 3 vsync output invert one bit that inverts the polarity of the vsync output. table 16 shows the effect of this option. table 16. vsync output polarity settings setting vsync output 0 invert 1 no invert the default setting for this register is 1. this option works on both the analog and digital interfaces.
ad9887a rev. b | page 38 of 52 0x0f 7 hsync input polarity a bit that must be set to indicate the polarity of the hsync signal that is applied to the pll hsync input. table 17. hsync input polarity (hspol) settings hspol function 0 active low 1 active high active low is the traditional negative-going hsync pulse. all timing is based on the leading edge of hsync, which is the falling edge. the rising edge has no effect. active high is inverted from the traditional hsync, with a positive-going pulse; therefore, timing is based on the leading edge of hsync, which is now the rising edge. the device operates if this bit is set incorrectly, but the internally generated clamp position, as established by clpos, will not be placed as expected, which might generate clamping errors. the power-up default value is hspol = 1. 0x0f 6 coast input polarity a bit to indicate the polarity of the coast signal that is applied to the pll coast input. table 18. coast input polarity (cstpol) settings cstpol function 0 active low 1 active high active low means that the clock generator ignores hsync inputs when coast is low and continues operating at the same nominal frequency until coast goes high. active high means that the clock generator ignores hsync inputs when coast is high and continues operating at the same nominal frequency until coast goes low. this function must be used with the coast polarity override bit (register 0x14, bit 1). the power-up default value is cstpol = 1. 0x0f 5 clamp input signal source a bit that determines the source of clamp timing. table 19. clamp input signal source (extclmp) settings extclmp function 0 internally generated clamp 1 externally provided clamp signal logic 0 enables the clamp timing circuitry controlled by clplace and cldur. the clamp position and duration is counted from the trailing edge of hsync. logic 1 enables the external clamp input pin. the three channels are clamped when the clamp signal is active. the polarity of clamp is determined by the clampol bit. the power-up default value is extclmp = 0. 0x0f 4 clamp input signal polarity a bit that determines the polarity of the externally provided clamp signal. table 20. clamp input signal polarity (extclmp) settings extclmp function 0 active low 1 active high logic 0 means that the circuit clamps when clamp is high and passes the signal to the adc when clamp is low. logic 1 means that the circuit clamps when clamp is low and passes the signal to the adc when clamp is high. the power-up default value is clampol = 1. 0x0f 3 external clock select a bit that determines the source of the pixel clock. table 21. external clock select (extclk) settings extclk function 0 internally generated clock 1 externally provided clock signal a logic 0 enables the internal pll that generates the pixel clock from an externally provided hsync. a logic 1 enables the external ckext input pin. in this mode, the pll divide ratio (plldiv) is ignored and the clock phase adjust (phase) is still functional. the power-up default value is extclk = 0. 0x0f 2 red clamp select a bit that determines whether the red channel is clamped to ground or to midscale. for rgb video, all three channels are referenced to ground. for ycbcr (or yuv), the y channel is referenced to ground, but the cbcr channels are referenced to midscale. clamping to midscale actually clamps to pin 118, r clamp v. table 22. red clamp select settings clamp function 0 clamp to ground 1 clamp to midscale (pin 118) the default setting for this register is 0.
ad9887a rev. b | page 39 of 52 0x0f 1 green clamp select a bit that determines whether the green channel is clamped to ground or to midscale. table 23. green clamp select settings clamp function 0 clamp to ground 1 clamp to midscale (pin 109) the default setting for this register is 0. 0x0f 0 blue clamp select a bit that determines whether the blue channel is clamped to ground or to midscale. table 24. blue clamp select settings clamp function 0 clamp to ground 1 clamp to midscale (pin 99) the default setting for this register is 0. mode control 2 0x10 7 data output clock invert (ckinv) a control bit for the inversion of the output data clocks (pin 134 and pin 135). this function only works for the digital interface. when not inverted, data is output upon the trailing edge of the data clock. see figure 37 through figure 40 for how this affects timing. table 25. data output clock invert (ckinv) settings ckinv function 0 not inverted 1 inverted the default for this register is 0. 0x10 6 pixel select this bit selects either one or two pixels per clock mode for the digital interface. it determines whether the output is from a single port (even port only) at the full data rate, or from two ports (both even and odd ports) at half the full data rate per port. logic 0 selects one pixel per clock (even port only). logic 1 selects two pixels per clock (both ports). see the digital interface timing diagrams ( figure 37 through figure 40 ) for visual representations of this function. note that this function operates exactly like the demux function on the analog interface. table 26. pixel select settings pixel select function 0 one pixel per clock 1 two pixels per clock the default for this register is 0. 0x10 5, 4 output drive these two bits select the drive strength for the high speed digital outputs (all data output and clock output pins). higher drive strength results in faster rise/fall times and enables easier capture of data in general. lower drive strength results in slower rise/fall times and reduces emi and digitally generated power supply noise. the exact timing specifications for each of these modes are specified in table 7 . table 27. output drive strength settings bit 5 bit 4 result 1 x high drive strength 0 1 medium drive strength 0 0 low drive strength the default for this register is 11. this option works on both the analog and digital interfaces. 0x10 3 power-down outputs (pdo) this bit can put the outputs into a high impedance mode. this applies to all outputs except sogout and refout. table 28. power-down output (pdo) settings pdo function 0 normal operation 1 three-state the default for this register is 0. this option works on both the analog and digital interfaces. 0x10 2 sync detect polarity this pin controls the polarity of the sync detect output pin (pin 136). table 29. sync detect polarity settings polarity function 0 activity = logic 1 output 1 activity = logic 0 output the default for this register is 0. this option works on both the analog and digital interfaces.
ad9887a rev. b | page 40 of 52 sync detection/active interface control 0x11 7 analog interface hsync detect this bit is used to indicate when activity is detected on the hsync input pin (pin 82). if hsync is held high or low, activity is not detected. table 30. analog interface hsync detection results detect function 0 no activity detected 1 activity detected figure 43 shows where this function is implemented. 0x11 6 analog interface sync-on-green detect this bit is used to indicate when sync activity is detected on the sync-on-green input pin (pin 108). table 31. analog interface sync-on-green detection results detect function 0 no activity detected 1 activity detected figure 43 shows where this function is implemented. warning: even if no sync is present on the green video input, normal video might trigger activity. 0x11 5 analog interface vsync detect this bit indicates when activity is detected on the vsync input pin (pin 81). if vsync is held high or low, activity is not detected. table 32. analog interface vsync detection results detect function 0 no activity detected 1 activity detected figure 43 shows where this function is implemented. 0x11 4 digital interface clock detect this indicates when activity is detected on the digital interface clock input. because this register is unreliable in certain applications, an external dvi clock detect shown in figure 28 is recommended. table 33. digital interface clock detection results detect function 0 no activity detected 1 activity detected figure 43 shows where this function is implemented. 0x11 3 active interface (ai) this bit indicates which interface should be active, analog or digital. it checks for activity on the analog and digital interfaces, then determines which should be active according to the conditions outlined in table 34 . specifically, analog interface detection is determined by oring bit 7, bit 6, and bit 5 from this register. digital interface detection is determined by bit 4 in this register. if both interfaces are detected, the user can deter- mine which has priority via bit 6 in register 0x12. the user can override this function via bit 7 in register 0x12. if the override bit is set to logic 1, this bit is forced to the set state of bit 6 in register 0x12. table 34. active interface results bits 7, 6, or 5 (analog detection) bit 4 (digital detection) override 1 ai 2, 3 0 0 0 soft power-down (seek mode) 0 1 0 1 1 0 0 0 1 1 0 bit 6 in register 0x12 x x 1 bit 6 in register 0x12 1 the override bit is bi t 7 in register 0x12. 2 ai = 0 means analog interface. 3 ai = 1 means digital interface. 0x11 2 active hsync (ahs) this bit determines which hsync to use for the analog interface, the hsync input or the sync-on-green. it uses bit 7 and bit 6 in this register for inputs when determining which should be active. similar to the previous bit, if both hsync and sync-on-green are detected, the user can deter- mine which has priority via bit 4 in register 0x12. the user can override this function via bit 5 in register 0x12. if the override bit is set to logic 1, this bit is forced to the set state of bit 4 in register 0x12. table 35. active hsync results bit 7 bit 6 (hsync detect) (sog detect) override 1 ahs 2, 3 0 0 0 bit 4 in register 0x12 0 1 0 1 1 0 0 0 1 1 0 bit 4 in register 0x12 x x 1 bit 4 in register 0x12 1 the override bit is bi t 5 in register 0x12. 2 ahs = 0 means hsync input. 3 ahs = 1 means sog input.
ad9887a rev. b | page 41 of 52 0x11 1 active vsync (avs) this bit determines which vsync to use for the analog interface, the vsync input or the sync separator output. if both vsync and composite sog are detected, vsync is selected. the user can override this function via bit 3 in register 0x12. if the override bit is set to logic 1, this bit is forced to the set state of bit 2 in register 0x12. table 36. active vsync results bit 5 (vsync detect) override 1 avs 2, 3 0 0 0 1 0 1 x 1 bit 2 in register 0x12 1 the override bit is bi t 3 in register 0x12. 2 avs = 0 means vsync input. 3 avs = 1 means sync separator. 0x12 7 active interface override (aio) set this bit (bit 3 in register 0x11) to logic 1 to override the automatic interface selection. when overriding the automatic interface selection, the active interface is set via bit 6 in this register. table 37. active interface override settings aio result 0 autodetermines the active interface 1 override, bit 6 determines the active interface the default for this register is 0. 12 6 active interface select (ais) this bit is used under two conditions. it is used to select the active interface when the override bit (bit 7) is set. alternately, it is used to determine the active interface when the override bit is not set, but both interfaces are detected. table 38. active interface select settings ais result 0 analog interface 1 digital interface the default for this register is 0. 0x12 5 active hsync override this bit is used to override the automatic hsync selection (bit 2 in register 0x11). to initiate, set this bit to logic 1. when overriding the automatic hsync selection, the active hsync is set via bit 4 in this register. table 39. active hsync override settings override result 0 autodetermines the active interface 1 override, bit 4 determines the active interface the default for this register is 0. 0x12 4 active hsync select this bit is used under two conditions. it is used to select the active hsync when the override bit (bit 5) is set. alternately, it is used to determine the active hsync when the override bit is not set, but both hsyncs are detected. table 40. active hsync select settings select result 0 hsync input 1 sync-on-green input the default for this register is 0. 0x12 3 active vsync override this bit is used to override the automatic vsync selection (bit 1 in register 0x11). to initiate this, set this bit to logic 1. when overriding the automatic vsync selection, the active interface is set via bit 2 in this register. table 41. active vsync override settings override result 0 autodetermines the active vsync 1 override, bit 2 determines the active vsync the default for this register is 0. 0x12 2 active vsync select this bit is used to select the active vsync when the override bit (bit 3) is set. table 42. active vsync select settings select result 0 vsync input 1 sync separator output the default for this register is 0. 0x12 1 coast select this bit is used to select which coast source is active, the coast input pin or vsync. if vsync is selected, users must decide whether to use the vsync input pin or the output from the sync separator (bit 3 and bit 2). table 43. coast select settings select result 0 coast input pin 1 vsync (see above text)
ad9887a rev. b | page 42 of 52 0x12 0 pwrdn this bit can be used to fully power down both interfaces of the chip. see the power management section for details on which blocks are actually powered down. note that the chip is unable to detect incoming activity while fully powered down. table 44. power-down settings select result 0 power down 1 normal operation the default for this register is 1. digital control 0x13 7:0 sync separator threshold this register is used to set the responsiveness of the sync separator. it sets the number of 5 mhz clock pulses the sync separator counts before toggling high or low. it works like a low-pass filter to ignore hsync pulses in order to extract the vsync signal. this register should be set to a number greater than the maximum hsync pulse width. the default for this register is 32. control bits 0x14 2 scan enable this register is used to enable the scan function. when this function is enabled, data can be loaded into the ad9887a outputs serially. the scan function utilizes three pins: scan in , scan out , and scan clk . these pins are described in the scan function section. table 45. scan enable settings scan enable result 0 scan function disabled 1 scan function enabled the default for scan enable is 0 (disabled). 0x14 1 coast input polarity override this register is used to override the internal circuitry that determines the polarity of the coast signal going into the pll. table 46. coast input polarity override settings override bit result 0 coast polarity determined by chip 1 coast polarity determined by user the default for coast polarity override is 0. 0x14 0 hsync input polarity override this register is used to override the internal circuitry that determines the polarity of the hsync signal going into the pll. table 47. hsync input polarity override setting override bit result 0 hsync input polarity determined by chip 1 hsync input polarity determined by user the default for hsync input polarity override is 0. 0x15 7 hsync input polarity status this bit reports the status of the hsync input polarity detection circuit. it can be used to determine the polarity of the hsync input. the location of the detection circuit is shown in the figure 43 . table 48. detected hsync input polarity status status result 0 hsync input polarity is negative. 1 hsync input polarity is positive. 0x15 6 vsync output polarity status this bit reports the status of the vsync output polarity detection circuit. it can be used to determine the polarity of the vsync input. the location of the detection circuit is shown in the figure 43 . table 49. detected vsync input polarity status status result 0 vsync input polarity is active low. 1 vsync input polarity is active high. 0x15 5 coast input polarity status this bit reports the status of the coast input polarity detection circuit. it can be used to determine the polarity of the coast input. the location of the detection circuit is shown in the figure 43 . table 50. detected coast input polarity status status result 0 coast input polarity is negative. 1 coast input polarity is positive. 0x16 7C3 sync-on-green slicer threshold this register allows the comparator threshold of the sync-on-green slicer to be adjusted. this register adjusts the comparator threshold in 10 mv steps. a setting of 0 results in a 330 mv threshold; a setting of 31 results in a 10 mv threshold. the default setting is 23, which corre- sponds to a threshold value of 70 mv.
ad9887a rev. b | page 43 of 52 0x17 7:0 precoast this register allows the coast signal to be applied prior to the vsync signal. this is necessary in cases where pre- equalization pulses are present. this register defines the number of edges that are filtered before vsync on a composite sync. the default is 0. 0x18 7:0 postcoast this register allows the coast signal to be applied following the vsync signal. this is necessary when postequalization pulses are present. this register defines the number of edges that are filtered after vsync on a composite sync. the default is 0. 0x19 7:0 test must be set to default. 0x1a 7:0 test must be set to 0x41 for proper operation. 0x1b 7:0 test must be set to 0x00 for autogain mode and 0x10 for manual-gain mode. 0x1c 7:3 test must be set to 00000*** for autogain mode and 00101*** for manual-gain mode. 0x1c 2 cbcr output order in 4:2:2 mode, the red and blue channels can be interchanged to help satisfy board layout or timing requirements, but the green channel must be configured for y. register 0x1c, bit 2, controls the order that the u/v (cbcr) data is output. if this bit is high, the red channel data precedes the blue channel data. if this bit is low, the blue channel data precedes the red channel data. see the example in table 51 . table 51. 4:2:2 input/output configuration channel input connection output format red y v/u if 0x1c bit 2 = 1; u/v if 0x1c bit 2 = 0 green y y blue u high impedance 0x1c 1 test bits must be set to 0 for standard input sampling. 0x1c 0 4:2:2 output mode select 4:2:2 mode can be used to reduce the number of data lines used from 24 to 16 for applications using yuv, ycbcr, or ypbpr graphics signals. see figure 27 for a timing diagram for this mode. table 52. 4:2:2 output mode select select output mode 1 4:4:4 0 4:2:2 0x1d 6 hdcp keys detected this bit indicates the presence of hdcp keys read from the external eeprom. table 53. hdcp key status select hdcp key status 1 hdcp keys present 0 hdcp keys not present 0x1e 7:0 test register must be set to 0xff for proper operation. 0x1f 7:0 test register must be set to 0x84 for proper operation. 0x20 7 hdcp a0 serial address bit this bit sets the value of the a0 bit for the ddc serial port. table 54. hdcp a0 serial address select serial address 1 a0 bit = 1, address = 0x76 0 a0 bit = 0, address = 0x74 the default setting is 0. 0x20 6 mda pin select this bit sets the function of pin 49 to mda when set at 1. table 55. mda pin select select output mode 1 pin 49 = mda for hdcp 0 pin 49 = ctl3 signal the default setting is 0. 0x20 5 analog input bandwidth control this bit controls the analog input bandwidth . table 56. analog input bandwidth control select input bandwidth 0 high analog input bandwidth 1 low analog input bandwidth the default setting 0.
ad9887a rev. b | page 44 of 52 0x20 4 mda/mcl three-state this bit allows the mda/mcl lines to be three-stated so that the hdcp key eeprom can be programmed in-circuit. table 57. mda/mcl three-state select mda/mcl output 1 normal operation 0 mda/mcl set to three-state the default setting is 0. 0x20 3 external oscillator this bit allows use of either the internal oscillator or an external one supplied on the a0 pin. table 58. external oscillator select select oscillator 1 use internal oscillator 0 use external oscillator on a0 pin the default setting is 0. 0x20 2 view hdcp mask this bit allows the hdcp mask to be output on the rgb channels. table 59. view hdcp mask select output mode 1 hdcp mask output to rgb channel 0 normal operation 0x21 7:0 test register set to 0x00 for autogain mode and 0x64 for manual- gain mode. 0x22 7:0 test register must be set to 0x00 for proper operation. 0x23 7:0 test register must be set to 0x2a for proper operation. 0x24 7:0 test register must be set to 0x00 for proper operation. 0x25 7:0 test register must be set to 0xf0 for proper operation. 0x26 7:0 test register must be set to 0xff for proper operation. 0x27 7:0 test register must be set to 0x0f for proper operation.
ad9887a rev. b | page 45 of 52 2-wire serial control port a 2-wire serial interface control port is provided. up to four ad9887a devices can be connected to the 2-wire serial interface, with each device having a unique address. the 2-wire serial interface comprises a clock (scl) and a bidirectional data (sda) pin. the analog flat panel interface acts as a slave for receiving and transmitting data over the serial interface. when the serial interface is not active, the logic levels on scl and sda are pulled high by external pull-up resistors. data received or transmitted on the sda line must be stable for the duration of the positive-going scl pulse. data on sda must change only when scl is low. if sda changes state while scl is high, the serial interface interprets that action as a start or stop sequence. there are five components to serial bus operation: ? start signal ? slave address byte ? base register address byte ? data byte to read or write ? stop signal when the serial interface is inactive (scl and sda are high), communication is initiated by sending a start signal. the start signal is a high-to-low transiti on on sda while scl is high. this signal alerts all slaved devices that a data transfer sequence is coming. the first eight bits of data transferred after a start signal comprise a 7-bit slave address (the first seven bits) and a single r/ w bit (the eighth bit). the r/ w bit indicates the direction of data transfer, reading from (1) or writing to (0) the slave device. if the trans- mitted slave address matches the address of the device (set by the state of the a1 and a0 input pins listed in table 60 ), the ad9887a acknowledges it by bringing sda low on the ninth scl pulse. if the addresses do not match, the ad9887a does not acknowledge it. table 60. serial port addresses bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 a 6 (msb) a 5 a 4 a 3 a 2 a 1 a 0 1 0 0 1 1 0 0 1 0 0 1 1 0 1 1 0 0 1 1 1 0 1 0 0 1 1 1 1 data transfer via serial interface for each byte of data read or written, the msb is the first bit of the sequence. if the ad9887a does not acknowledge the master device during a write sequence, the sda remains high so that the master can generate a stop signal. if the master device does not acknowledge the ad9887a during a read sequence, the ad9887a interprets this as the end of the data. the sda remains high so that the master can generate a stop signal. writing data to a specific control register of the ad9887a requires writing to its 8-bit address after the slave address has been established. this control register address is the base address for subsequent write operations. the base address auto- increments by one for each byte of data written after the data byte intended for the base address is established. if more bytes are transferred than there are available addresses, the address does not increment and remains at its maximum value of 0x1d. any base address higher than 0x1d does not produce an acknowledge signal. data is read from the control registers of the ad9887a in a similar manner. reading requires two data transfer operations. the base address must be written with the r/ w bit of the slave address byte low to set up a sequential read operation. reading begins at the previously established base address with the r/ w bit of the slave address byte high. the address of the read register auto-increments after each byte is transferred. to terminate a read/write sequence to the ad9887a, a stop signal must be sent. a stop signal comprises a low-to-high transition of sda while scl is high. the timing for the read/write operations is shown in figure 41 ; a typical byte transfer is shown in figure 42 . a repeated start signal occurs when the master device driving the serial interface generates a start signal without first generating a stop signal to terminate the current communication. this is used to change the mode of communication (read, write) between the slave and master without releasing the serial interface lines.
ad9887a rev. b | page 46 of 52 sda scl t dho t dsu t stasu t stah t buff t dal t dah t stosu 02838-039 figure 41. serial port r/ w timing bit 7 sda scl ack bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 02838-040 figure 42. serial interfacetypical byte transfer
ad9887a rev. b | page 47 of 52 serial interface read/write examples write to one of the following control registers: ? start signal ? slave address byte (r/ w bit = low) ? base address byte ? data byte to base address ? stop signal write to four of the following consecutive control registers: ? start signal ? slave address byte (r/ w bit = low) ? base address byte ? data byte to base address ? data byte to (base address + 1) ? data byte to (base address + 2) ? data byte to (base address + 3) ? stop signal read from one of the following control registers: ? start signal ? slave address byte (r/ w bit = low) ? base address byte ? start signal ? slave address byte (r/ w bit = high) ? data byte from base address ? stop signal read from four of the following consecutive control registers: ? start signal ? slave address byte (r/ w bit = low) ? base address byte ? start signal ? slave address byte (r/ w bit = high) ? data byte from base address ? data byte from (base address + 1) ? data byte from (base address + 2) ? data byte from (base address + 3) ? stop signal table 61. control of sync block muxes via the serial register mux no. serial bus, control bit control bit state result 1 and 2 0x12, bit 4 0 pass hsync 1 pass sync-on-green 3 0x12, bit 1 0 pass coast 1 pass vsync 4 0x12, bit 2 0 pass vsync 1 pass sync separator signals 5, 6, and 7 0x11, bit 3 0 pass digital interface signals 1 pass analog interface signals
ad9887a rev. b | page 48 of 52 theory of operationsync processing sync stripper the purpose of the sync stripper is to extract the sync signal from the green graphics channel. a sync signal is not present on all graphics systems, only those with sync-on-green. the sync signal is extracted from the green channel in a two-step process. first, the sog input is clamped to its negative peak (typically 0.3 v below the black level). next, the signal goes to a comparator with a trigger level that is 0.15 v above the clamped level. the output signal is typically a composite sync signal containing both hsync and vsync. sync separator a sync separator extracts the vsync signal from a composite sync signal by using a low-pass filter-like or integrator-like operation. it works on the idea that the vsync signal stays active much longer than the hsync signal. therefore, it rejects any signal shorter than a threshold value, which is somewhere in the range between an hsync pulse width and a vsync pulse width. the sync separator on the ad9887a is simply an 8-bit digital counter with a 5 mhz clock. it works independently of the polarity of the composite sync signal. (polarities are determined elsewhere on the chip.) the basic idea is that the counter counts up when hsync pulses are present. since hsync pulses are relatively short in width, the counter only reaches a value of n before the pulse ends. it then starts counting down, eventually reaching 0 before the next hsync pulse arrives. the specific value of n varies among video modes, but is always less than 255. for example, with a 1 s width hsync, the counter only reaches 5 (1 s/200 ns = 5). when vsync is present on the composite sync, the counter also counts up. because the vsync signal is much longer, it counts to a higher number m. for most video modes, m is at least 255. therefore, vsync can be detected on the composite sync signal by detecting when the counter counts to higher than n. the specific count that triggers detection, the threshold count (t), can be programmed through the serial register 0x0f. once vsync is detected, there is a similar process to detect when it becomes inactive. upon detection, the counter first resets to 0, then counts up when vsync disappears. similar to the previous case, it detects the absence of vsync when the counter reaches t. in this way, it rejects noise and/or serration pulses. once vsync is detected to be absent, the counter resets to 0 and begins the cycle again. sync stripper negative peak clamp comp sync sog hsync in hsync out pixel clock mux 1 sync separator integrator vsync sog out hsync out vsync out mux 4 vsync in 1/s pll hsync activity detect ad9887a clock generator coast coast 02838-041 activity detect activity detect polarity detect polarity detect polarity detect mux 2 mux 3 polarity invert figure 43. sync processing block diagram
ad9887a rev. b | page 49 of 52 pcb layout recommendations the ad9887a is a high performance, high speed analog device. to optimize its performance, it is important to have a well laid out board. the following is a guide for designing a board using the ad9887a. analog interface inputs using the following layout techniques on the graphics inputs is extremely important. ? minimize the trace length running into the graphics inputs. this is accomplished by placing the ad9887a as close as possible to the graphics vga connector. long input trace lengths are undesirable because they pick up noise from the board and other external sources. ? place the 75 termination resistors as close to the ad9887a chip as possible. any additional trace length between the termination resistors and the input of the ad9887a increases the magnitude of reflections, which corrupts the graphics signal. ? use 75 matched impedance traces. trace impedances other than 75 also increase the chance of reflections. the ad9887a has very high input bandwidth (330 mhz). although this is desirable for acquiring a high resolution pc graphics signal with fast edges, it means that it also captures any high frequency noise present. therefore, it is important to reduce the amount of noise coupled to the inputs. avoid running any digital traces near the analog inputs. due to the high bandwidth of the ad9887a, sometimes low-pass filtering the analog inputs can help reduce noise. (for many applications, filtering is unnec- essary.) experiments have shown that placing a series ferrite bead in front of the 75 termination resistor can filter out excess noise. specifically, the part used was the #2508051217z0 from fair-rite, but each application might work best with a different bead value. alternatively, placing a 100 to 120 resistor between the 75 termination resistor and the input coupling capacitor can also be beneficial. digital interface inputs each differential input pair (rx0+, rx0?, rxc+, rxc?, and so on) should be routed together using 50 strip line routing techniques kept as short as possible. no other components should be placed on these inputs (for example, no clamping diodes). every effort should be made to route these signals on a single layer (component layer) with no vias. power supply bypassing it is recommended to bypass each power supply pin with a 0.1 f capacitor. the exception is when two or more supply pins are adjacent to each other. for these groupings of powers/grounds, it is only necessary to have one bypass capacitor. the fundamental idea is to have a bypass capacitor within about 0.5 cm of each power pin. also, avoid placing the capacitor on the side of the pc board opposite from the ad9887a, because this interposes resistive vias in the path. the bypass capacitors should physically be located between the power plane and the power pin. current should flow from the power plane to the capacitor to the power pin. do not make the power connection between the capacitor and the power pin. placing a via underneath the capacitor pads, down to the power plane, is generally the best approach. it is particularly important to maintain low noise and good stability of pv d (the clock generator supply). abrupt changes in pv d can result in similarly abrupt changes in sampling clock phase and frequency. this can be avoided by careful regulation, filtering, and bypassing. it is highly desirable to provide separate regulated supplies for each of the analog circuitry groups (v d and pv d ). some graphics controllers use substantially different levels of power when active (during active picture time) and when idle (during horizontal and vertical sync periods). this can result in a measurable change in the voltage supplied to the analog supply regulator, which can in turn produce changes in the regulated analog supply voltage. this can be mitigated by regulating the analog supply, or at least pv d , from a different, cleaner power source (for example, from a 12 v supply). it is recommended to use a single ground plane for the entire board. experience shows that noise performance is the same or better with a single ground plane. using multiple ground planes can be detrimental because each separate ground plane is smaller and can result in long ground loops. in some cases, using separate ground planes is unavoidable. for these cases, it is recommended to place at least a single ground plane under the ad9887a. the location of the split should be at the receiver of the digital outputs. for these cases, it is even more important to place components wisely because the current loops are much longer, and current takes the path of least resistance. an example of a current loop follows. a n a l o g g r o u n d p l a n e p o w e r p l a n e a d 9 8 8 7 a d i g i t a l o u t p u t t r a c e d i g i t a l g r o u n d p l a n e d i g i t a l d a t a r e c e i v e r 02838-042 figure 44. example of a current loop
ad9887a rev. b | page 50 of 52 pll place the pll loop filter components as close as possible to the filt pin. do not place any digital or other high frequency traces near these components. use the values suggested in the specifications section with 10% tolerances or less. outputsboth data and clocks try to minimize the trace length that the digital outputs must drive. longer traces have higher capacitance, requiring more current and causing more internal digital noise. shorter traces reduce the possibility of reflections. adding a series resistor with a value of 22 to 100 can suppress reflections, reduce emi, and reduce the current spikes inside of the ad9887a. however, if 50 traces are used on the pcb, the data outputs should not need these resistors. a 22 resistor on the datack output should provide good impedance matching that further reduces reflections. if emi or current spiking is a concern, it is recommended to use a lower drive strength setting. if series resistors are used, place them as close as possible to the ad9887a pins, but try not to add vias or extra length to the output trace. if possible, limit the capacitance that each of the digital outputs drives to less than 10 pf. this can be accomplished easily by keeping traces short and connecting the outputs to only one device. loading the outputs with excessive capacitance increases the current transients inside the ad9887a, creating digital noise on the power supplies. digital inputs the digital inputs on the ad9887a are designed to work with 3.3 v signals. any noise in the hsync input trace produces jitter in the system. therefore, minimize the trace length and do not run any digital or other high frequency traces near it. voltage reference the voltage reference should be bypassed with a 0.1 f capacitor. place it as close as possible to the ad9887a pin. make the ground connection as short as possible. refout is easily connected to refin with a short trace. avoid making this trace longer than necessary. when using an external reference, the refout output, although unused, still needs to be bypassed with a 0.1 f capacitor to avoid ringing.
ad9887a rev. b | page 51 of 52 outline dimensions compliant to jedec standards ms-022dd-1 31.45 31.20 sq 30.95 0.65 bsc lead pitch 0.40 0.22 121 160 1 120 40 80 81 top view (pins down) pin 1 41 4.10 max 1.03 0.88 0.73 seating plane 28.20 28.00 sq 27.80 view a 3.60 3.40 3.20 0.50 0.25 7 0 0.10 coplanarity view a rotated 90 ccw 10 6 2 0.23 0.11 lead pitch figure 45. 160-lead metric quad flat package [mqfp] (s-160) dimension shown in millimeters ordering guide model max speed (mhz) analog dvi temperature range package description package option ad9887aks-100 100 100 0c to 70c 160-lead metric quad flatpack s-160 ad9887aksz-100 1 100 100 0c to 70c 160-lead metric quad flatpack s-160 ad9887aks-140 140 140 0c to 70c 160-lead metric quad flatpack s-160 ad9887aksz-140 1 140 140 0c to 70c 160-lead metric quad flatpack s-160 ad9887aks-170 170 170 0c to 70c 160-lead metric quad flatpack s-160 AD9887AKSZ-170 1 170 170 0c to 70c 160-lead metric quad flatpack s-160 ad9887a/pcb evaluation kit 1 z = rohs compliant part.
ad9887a rev. b | page 52 of 52 t notes ?2003C2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. c02838-0-3/07(b) ttt

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